CS5535 datasheet(487/555 Pages) NSC

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PMC Register Descriptions (Continued)

5.18.3 PM Support Registers

The registers listed in this sub-section are not ACPI registers, but are used to support power management implementation.

5.18.3.1

PM Sleep Start Delay (PM_SSD)

5.18.3.2

PM Sleep Control X Assert Delay and Enable (PM_SCXA)

Reads always return the value written.

PMS I/O Offset

00h

Type

R/W

Reset Value

0000h

PM_SSD Register Map

987

6543

210

RSVD

SLP_DELAY

PM_SSD Bit Descriptions

Bit

Name

Description

SLP_EN_INDIC

Sleep Enable Indicator. If SLP_EN (ACPI I/O Offset 08h[13]) was written to a 1, then

this bit reads high. If this bit is written to a 1, the Sleep sequence is aborted. Writing a 0

to this bit has no effect. This bit always clears on a Sleep or Standby wakeup.

RSVD

Reserved. By convention write 0. Reads return value written.

SLP_WRT_EN

Sleep Write Enable. Must be high in order to change bits 12 and [11:0]

(SLP_DELAY_EN and SLP_DELAY). Reads of this bit always return 0.

SLP_DELAY_EN

Sleep Delay Enable. Must be high to enable the delay specified in bits [11:0]

(SLP_DELAY). Reads return value written.

11:0

SLP_DELAY

Sleep Delay. Indicates the number of 3.57954 MHz clock edges to wait before begin-

ning the Sleep or Standby process as defined by SLP_EN (ACPI I/O Offset 08h[13]).

Bit 12 (SLP_DELAY_EN) must be high to enable this delay. Reads return the value writ-

ten.

PMS I/O Offset

04h

Type

R/W

Reset Value

00000000h

PM_SCXA Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

SLPX_DELAY

PM_SCXA Bit Descriptions

Bit

Name

Description

RSVD

Reserved. By convention write 0, but may write anything.

SLPX_EN

Sleep X Assert and Delay Enable. Must be high to assert the SLEEP_X ball and to

enable its assert delay specified in bits [29:0] (SLPX_DELAY).

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