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CS5535 Datasheet(PDF) 489 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535 Datasheet(HTML) 489 Page - National Semiconductor (TI)

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PMC Register Descriptions (Continued)
5.18.3.5
PM Sleep Clock Delay and Enable (PM_SCLK)
Reads always return the value written.
PM_OUT_SLPCTL Bit Descriptions
Bit
Name
Description
31
RSVD
Reserved. By convention write 0, but may write anything.
30
PCI_IDE_OUT_
SLP
PCI/IDE Output Sleep Control. Allows the delay specified in bits [29:0]
(PCI_IDE_OUT_SLP_DELAY) to turn off PCI/IDE outputs as listed in Table 3-11
"Sleep Driven PCI Signals" and Table 3-12 "Sleep Driven IDE Signals" on page 72.
Individual enables exist for PCI (PCI GLD_MSR_PM, MSR 51000004h[49:48]) and
IDE (IDE GLD_MSR_PM, MSR 51300004h[49:48]). Output control immediately
enables the PCI/IDE outputs when SUSP# de-asserts.
0: Disable.
1: Enable.
29:0
PCI_IDE_OUT_
SLP_DELAY
PCI/IDE Output Sleep Control Delay. Indicates the number of 3.57954 MHz clock
edges to wait from Sleep wakeup before PCI/IDE outputs are disabled. Bit 30
(PCI_IDE_OUT_SLP) must be high to enable this delay.
The PCI/IDE outputs will not turn off if this delay is larger than SLPCLK_DELAY (PMS
I/O Offset 10h[29:0]). This is only true if SLPCLK_EN is enabled (PMS I/O Offset
10h[30] = 1).
PMS I/O Offset
10h
Type
R/W
Reset Value
00000000h
PM_SCLK Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
SLPCLK_DELAY
PM_SCLK Bit Descriptions
Bit
Name
Description
31
RSVD
Reserved. By convention write 0, but may write anything.
30
SLPCLK_EN
Sleep Clock Delay Enable. Must be high to assert SLP_CLK_EN# and enable its
assert delay specified in bits [29:0] (SLPCLK_DELAY). Use of this control is required
but not sufficient to enter the Standby state.
WARNING: Using this control immediately turns off all system clocks except the 32 kHz
RTC clock.
29:0
SLPCLK_DELAY
Sleep Clock Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait
from the assertion of SUSPA# before asserting SLP_CLK_EN#. Bit 30 (SLPCLK_EN)
must be high to enable this delay.
There is NOT a de-assert delay. The wakeup event causes SLP_CLK_EN# to de-
assert combinatorially from the wakeup event. This event is called Sleep wakeup. The
concept of a Sleep wakeup applies even if Sleep Clock is not used.



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