CS5535 datasheet(485/555 Pages) NSC

485 / 555 page

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485

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PMC Register Descriptions (Continued)

5.18.2.7

General Purpose Events Enable 0 (PM_GPE0_EN)

PM_GPE0_EN is the Enable register for General Purpose Events. Reads always return the value written. By convention,

bits [23:0] are associated with the Working domain while bits [31:24] are associated with the Standby domain. During

Standby, bits [23:0] are unconditionally cleared. PME status can be read via the corresponding FLAG bit in the

PM_GPE0_STS register (ACPI I/O Offset 18h).

USBC1_PME_

FLAG

USB Controller #1 PME Flag. If high, this bit records that a PME occurred via USB

Controller #1. Both this bit and the corresponding enable bit in

PM_GPE0_EN (ACPI

I/O Offset 1Ch[5]) must be high in order for this PME to be passed on to the system.

Write 1 to clear; writing 0 has no effect.

UART2_PME_

FLAG

UART #2 PME Flag. If high, this bit records that a PME occurred via UART #2. Both

this bit and the corresponding enable bit in

PM_GPE0_EN (ACPI I/O Offset 1Ch[4])

must be high in order for this PME to be passed on to the system. Write 1 to clear; writ-

ing 0 has no effect.

UART1_PME_

FLAG

UART #1 PME Flag. If high, this bit records that a PME occurred via UART #1. Both

this bit and the corresponding enable bit in

PM_GPE0_EN (ACPI I/O Offset 1Ch[3])

must be high in order for this PME to be passed on to the system. Write 1 to clear; writ-

ing 0 has no effect.

SMB_PME_

FLAG

SMB PME Flag. If high, this bit records that a PME occurred via the SMB. Both this bit

and the corresponding enable bit in

PM_GPE0_EN (ACPI I/O Offset 1Ch[2]) must be

high in order for this PME to be passed on to the system. Write 1 to clear; writing 0 has

no effect.

PIC_ASMI_PME_

FLAG

PIC ASMI PME Flag. If high, this bit records that a PME occurred due to a PIC ASMI.

Both this bit and the corresponding enable bit in

PM_GPE0_EN (ACPI I/O Offset

1Ch[1]) must be high in order for this PME to be passed on to the system. Write 1 to

clear; writing 0 has no effect.

PIC_IRQ_PME_

FLAG

PIC Interrupt PME Flag. If high, this bit records that a PME occurred due to a PIC

Interrupt. Both this bit and the corresponding enable bit in

PM_GPE0_EN (ACPI I/O

Offset 1Ch[0]) must be high in order for this PME to be passed on to the system. Write

1 to clear; writing 0 has no effect.

ACPI I/O Offset

1Ch

Type

R/W

Reset Value

00000000h

PM_GPE0_EN Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

RSVD

PM_GPE0_EN Bit Descriptions

Bit

Name

Description

GPIOM7_PME_

GPIO IRQ/PME Mapper Bit 7 PME Enable. When set high, this bit enables the gener-

ation of a PME to the system if a PME occurs via bit 7 of the GPIO IRQ/PME mapper.

Write this bit low to disable the generation of a PME from this source.

PM_GPE0_STS Bit Descriptions

Bit

Name

Description

CS5535 Datasheet(PDF) 485 Page - National Semiconductor (TI)

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