CS5535 datasheet(492/555 Pages) NSC

492 / 555 page

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492

Revision 0.8

PMC Register Descriptions (Continued)

5.18.3.9

PM PCI and IDE Input Sleep Control (PM_IN_SLPCTL)

Reads always return the value written.

5.18.3.10 PM Working De-assert Delay and Enable (PM_WKD)

Reads always return the value written, except for RSVD bits [29:20].

PMS I/O Offset

20h

Type

R/W

Reset Value

00000000h

PM_IN_SLPCTL Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

PCI_IDE_IN_SLP_DELAY

PM_IN_SLPCTL Bit Descriptions

Bit

Name

Description

RSVD

Reserved. By convention write 0, but may write anything.

PCI_IDE_IN_SLP

PCI/IDE Input Sleep Control. Allows the delay specified in bits [29:0]

(PCI_IDE_IN_SLP_DELAY) to turn off PCI/IDE inputs as listed in Table 3-11 "Sleep

Driven PCI Signals" and Table 3-12 "Sleep Driven IDE Signals" on page 72. Individual

enables exist for PCI (PCI GLD_MSR_PM, MSR 51000004h[49:48]) and IDE (IDE

GLD_MSR_PM, MSR 51300004h[49:48]).

0: Disable.

1: Enable.

29:0

PCI_IDE_IN_SLP

_DELAY

PCI/IDE Input Sleep Control Delay. Indicates the number of 3.57954 MHz clock

edges to wait from Sleep wakeup before PCI/IDE inputs are disabled. Bit 30

(PCI_IDE_IN_SLP) must be high to enable this delay.

PMS I/O Offset

30h

Type

R/W

Reset Value

00000000h

PM_WKD Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

RSVD

WORKING_DEASSERT_DELAY

CS5535 Datasheet(PDF) 492 Page - National Semiconductor (TI)

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