CS5535 datasheet(495/555 Pages) NSC

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PMC Register Descriptions (Continued)

5.18.3.13 PM Working Auxiliary Assert Delay from Standby Wakeup (PM_WKXA)

Reads always return the value written, except for RSVD bits [29:20].

5.18.3.14 PM Fail-Safe Delay and Enable (PM_FSD)

Reads always return the value written, except for RSVD bits [29:20].

19:0

RESET_DELAY

Reset De-assert Delay. Indicates the number of 32 kHz clock edges to continue

asserting RESET_OUT# from Standby Wakeup. Default value is 8 ms. This delay starts

only if the RESET_WORK# input is de-asserted and the internal Low Voltage Detect

circuit detects normal operating voltages on VCORE. (Default = 00100h.) (See Section

3.6 "Reset Considerations" on page 58 for further details regarding reset conditions.)

Bit 30 (RESET_EN) must be high to enable this delay.

Reset will be applied to the system for the longer of this value or until the internal Low

Voltage Detect circuit detects normal operating voltages on VCORE

PMS I/O Offset

3Ch

Type

R/W

Reset Value

00000000h

PM_WKXA Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

RSVD

WORK_AUX_DELAY

PM_WKXA Bit Descriptions

Bit

Name

Description

WORK_AUX_

LOCK

Working Auxiliary Lock. After this bit is set, the value in this register can not be

changed until RESET_STAND# is applied.

WORK_AUX_EN

Working Auxiliary Delay Enable. Must be high to enable the delay specified in bits

[19:0] (WORK_AUX_DELAY). If this bit is low, the WORK_AUX output is uncondition-

ally asserted at Standby wakeup. If WORK_AUX was not de-asserted going into

Standby, then this control is a “don’t care”.

29:20

RSVD

Reserved. By convention write 0, but may write anything. Reads return 0.

19:0

WORK_AUX_

DELAY

Working Auxiliary Assert Delay. Indicates the number of 32 kHz clock edges to wait

from Standby wakeup before asserting the WORK_AUX output. Bit 30

(WORK_AUX_EN) must be high to enable this delay.

May be programmed to assert before or after RESET_OUT# de-asserts.

The Standby wakeup event is not recognized until Normal (NWKD) or Abnormal

(AWKD) to Work Delay expires, if those delays are enabled. (See PMS I/O Offset 4Ch

and 50h for details regarding the NWKD and AWKD registers.)

PMS I/O Offset

40h

Type

R/W

Reset Value

00000000h

PM_RD Bit Descriptions (Continued)

Bit

Name

Description

CS5535 Datasheet(PDF) 495 Page - National Semiconductor (TI)

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