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CS5535 Datasheet(PDF) 534 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 534 Page - National Semiconductor (TI) |
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534 / 555 page ![]() www.national.com 534 Revision 0.8 Electrical Specifications (Continued) 6.3.3 PCI and Related Signals The signals detailed in this sub-section use a “PCI” buffer type except SUSP#, SUSPA#, and RESET_OUT# they use types “Q3” and “Q7” respectively. For a detailed explana- tion of buffer types, see Table 2-4 "Buffer Type Character- istics" on page 28. In this subsection, unless otherwise noted: • All timing specifications are specified under the oper- ating conditions listed in Table 6-3 on page 526 (i.e., VCORE and VCORE_VSB = All; VIO and VIO_VSB = All; TCASE = All). • Signals are referenced to PCI_CLK low-to-high edge. • Signal and test parameters are defined in Figure 6-2 "AC Reference Timing and Test Definition" on page 530. Table 6-9. PCI, SUSP#, SUSPA#, and RESET_OUT# Timing Parameters Signal Parameter Min Max Units Comment/Condition PCI_INTA# (GPIO0) PCI_INTB# (GPIO7) Async Input NA NA ns No clock reference. See Section 6.3.13 "GPIO Signaling" on page 548. REQ# tVAL 2 6 ns Note 1. GNT# tSETUP 5NA ns tHOLD 0NA ns CBE[3:0]#, DEVSEL#, FRAME#, TRDY#, IRDY#, STOP#, PAR, AD[31:0] tVAL 2 6 ns Applies when signal is an output. Note 1. tFLOAT NA 8 ns Applies when signal is an output. Note 2. tENABLE 2 NA ns Applies when signal is an output. Note 3. tSETUP 3 NA ns Applies when signal is an output. tHOLD 0NA ns SUSP# tVAL 1 6 ns Note 1. RESET_OUT# tVAL 3 10 ns Note 4. SUSPA# tSETUP 3NA ns tHOLD 0NA ns Note 1. tVAL min times with load of: 10 pF cap to ground. tVAL max times with load of: 35 pF cap to ground. Note 2. tFLOAT with the load of: 10 pF cap to ground. Note 3. tENABLE with the load of: 10 pF cap to ground. Note 4. tVAL min times with load of: 10 pF cap to ground tVAL max times with load of: 50 pF cap to ground. |
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