CS5535 datasheet(535/555 Pages) NSC

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Electrical Specifications (Continued)

6.3.4

IDE Signals in IDE Mode

The signals detailed in this sub-section use an “IDE” buffer

type. For a detailed explanation of buffer types, see Table

2-4 "Buffer Type Characteristics" on page 28.

In this subsection, unless otherwise noted:

• All timing specifications are specified under the oper-

ating conditions listed in Table 6-3 on page 526 (i.e.,

VCORE and VCORE_VSB = All; VIO and VIO_VSB = All;

TCASE = All).

• Signals are referenced to MHZ66_CLK low-to-high

edge.

• Signal and test parameters are defined in Figure 6-2

"AC Reference Timing and Test Definition" on page 530.

Table 6-10. IDE Register, PIO, and Multiword DMA Timing Parameters

Signal

Parameter

Min

Max

Units

Comment/Condition

IDE_CS[1:0]#,

IDE_IOW0,

IDE_AD[2:0],

IDE_RST#,

IDE_DACK0#

tVAL

IDE_DACK0# is only used for DMA.

Note 1 and Note 2.

IDE_IOR0#

tVAL

3•

Note 1 and Note 2.

IDE_DATA[15:0] for Write

Note 3.

IDE_DATA[15:0] for Read

Note 4 and Note 5.

IDE_RDY0,

IDE_IRQ0,

IDE_DREQ0#

Async Input

No clock reference. Note 6.

IDE_IRQ0 and IDE_DREQ0# are

only used for DMA.

Note 1. Per the ATA/ATAPI-5 spec, these signals utilize Output Reference Timing (see Figure 6-3 on page 531) relative to

IDE_IOR0# and IDE_IOW0#. However, the IDE Controller uses the MHZ66_CLK edges to make output changes,

that when taken together, meet all the timing requirements of the referenced spec. Therefore, tVAL times are spec-

ified and tested relative to the MHZ66_CLK.

Note 2. tVAL min times with load of: 15 pF cap to ground.

tVAL max times with load of: 40 pF cap to ground.

Note 3. Per the ATA/ATAPI-5 spec, IDE_DATA write signals utilize Output Reference Timing (see Figure 6-3 on page 531)

relative to IDE_IOW0#. However, the IDE Controller uses the MHZ66_CLK edges to make output changes, and

when taken together, meet all the timing requirements of the referenced spec. See Figure 6-5 "IDE Data In Timing

Non-UltraDMA" on page 536.

Note 4. Per the ATA/ATAPI-5 spec, these signals utilize Input Reference Timing (see Figure 6-4 on page 531) relative to

IDE_IOR0#. However, the IDE Controller samples the inputs with the MHZ66_CLK at the appropriate points in time

to meet all the timing requirements of the referenced spec.

Note 5. See Figure 6-5 "IDE Data In Timing Non-UltraDMA". As indicated in Note 4, IDE_DATA[15:0] read input is specified

relative to the low-to-high edge of IDE_IOR0#. However, the implementation meets a tighter test spec referenced

to the low-to-high edge of the MHZ66_CLK.

Note 6. For IDE_IRQ0, GPIO2 configured: Aux In and Input Enable = 1; Output Enable, Aux Out 1, and Aux Out 2 = 0.

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