CS5535 datasheet(537/555 Pages) NSC

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Electrical Specifications (Continued)

Figure 6-6. IDE UltraDMA Data Out Timing

Table 6-11. IDE UltraDMA Data Out Timing Parameters

Signal

Parameter

Min

Max

Units

Comment/Condition

IDE_DACK0#

IDE_HDMA_DS,

IDE_STOP,

IDE_IOW0#

tVAL

In Ultra DMA/33 mode, the

IDE_IOR0# signal is redefined as

IDE_HDMA_DS.

Note 1 and Note 2.

IDE_DATA[15:0]

tVAL

See Notes

Note 2 and Note 3.

IDE_DREQ0

Async Input

No clock reference. Note 4.

IDE_DDMA_RDY

Async Input

In Ultra DMA/33 mode, the

IDE_RDY0 signal is redefined as

IDE_DDMA_RDY.

Note 4.

IDE_IRQ0

Async Input

Note 4 and Note 5.

Note 1. Per the ATA/ATAPI-5 spec, these signals utilize Output Reference Timing (see Figure 6-3 on page 531) relative to

IDE_IOR0# and IDE_IOW0#. However, the IDE Controller uses the MHZ66_CLK edges to make output changes,

that when taken together, meet all the timing requirements of the referenced spec. Therefore, tVAL times are spec-

ified and tested relative to the MHZ66_CLK.

Note 2. tVAL min times with load of: 15 pF cap to ground.

tVAL max times with load of: 40 pF cap to ground.

Note 3. This signal uses Output Reference Timing (see Figure 6-3 on page 531). Figure 6-6 illustrates IDE_HDMA_DS and

IDE_DATA[15:0] relationship.

Note 4. Per the ATA/ATAPI-5 spec, these signals utilize Input Reference Timing (see Figure 6-4 on page 531) relative to

IDE_IOR0#. However, the IDE Controller samples the inputs with the MHZ66_CLK at the appropriate points in time

to meet all the timing requirements of the referenced spec.

Note 5. For IDE_IRQ0, GPIO2 configured: AUX_IN and Input Enable = 1; Output Enable, AUX_OUT_1, and AUX_OUT_2

= 0.

IDE_HDMA_DS

IDE_DATA[15:0]

tVAL_M = 6 ns

tVAL_P = 6 ns

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