NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
18
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in pre-
vious DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto
Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8
µs (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated
as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self
Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can
be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning
high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of
any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200
clock cycles before applying any other command.
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