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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
38
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS
Latency = 2; Burst Length = 8)
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
Don’t Care
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
Read
Write
NOP
CK
CK
Command
Address
BAa, COL b
BAa, COL n
tWTR
DI a-b
DQS
DQ
CL = 2
tDQSS (min)
DM
1
2
2
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
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