35 / 78 page
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
35
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Random Write Cycles (Burst Length = 2, 4 or 8)
T1
T2
T3
T4
T5
tDQSS (max)
Maximum DQSS
Write
Write
Write
Write
Write
DI a-b
DI a-n
DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.
DI a-b’
DI a-x
DI a-x’
DI a-n’
DI a-a
DI a-a’
CK
CK
Command
Address
DQS
DQ
DM
Don’t Care
BAa, COL b
BAa, COL x
BAa, COL n
BAa, COL a
BAa, COL g
T1
T2
T3
T4
T5
Minimum DQSS
Write
Write
Write
Write
Write
DI a-b
DI a-n
DI a-b’
DI a-x
DI a-x’
DI a-n’
DI a-a
DI a-a’
CK
CK
Command
Address
DQS
DQ
DM
BAa, COL b
BAa, COL x
BAa, COL n
BAa, COL a
BAa, COL g
tDQSS (min)
DI a-g
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
