MP5048

– 60V, 15A, 7mΩ RDS(ON) HOT-SWAP INTELLI-FUSE SOLUTION

MP5048 Rev. 1.1

www.MonolithicPower.com

16

4/30/2021

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© 2021 MPS. All Rights Reserved.

If VOUT drops below 20% of VIN during start-up

and the power FET current is regulated by the

VCLREF SS limit for the SCP timer, the power FET

turns off and FAULT is pulled low (see Figure 10).

If no fault occurs, the MP5048 follows the normal

start-up sequence, and the voltage rises on the

output of the device based on the SS rate.

t

Turn On SCP Timer

4V

2.4V

3.5µs Hold

7.5µs Hold

MP5048 UVLO

FAULT

VOUT

ON

TIMER

SS Limit

VCLREF

Insertion Delay

VCC

40µA

2µA

VCS

<20% of VIN

4V

3.5µs Hold

Figure 10: MP5048 Turn On SCP Time

An over-current condition occurs if the current

through the MP5048 reaches the configured

threshold and is held for the configured over-

current protection (OCP) time.

When

VCS

reaches

the

CLREF

voltage

(VCLREF_NORM), a 40μA source charges the

capacitor on the TIMER pin. As long as VCS

equals VCLREF, the current charges up the

capacitor. If the voltage on the TIMER pin

reaches the trip threshold (0.6V), the power FET

turns off and the FAULT pin is de-asserted to

indicate OCP has occurred (see Figure 11).

t

FAULT

OCP Delay

TIMER

0.6V

VCLREF_NORM

VCS

VOUT

40µA

Turn Off Here

Figure 11: MP5048 OCP Time

The timer allows the OCP time to be adjusted so

that the system can endure a current transient

event without forcing a shutdown. A current

transient can cause a current that exceeds the

OCP threshold for a small amount of time;

adjusting the timer can accommodate this brief

OC condition.

If a fault occurs, the FAULT pin is pulled low to

indicate a fault condition has occurred. If the

MODE pin is set to auto-retry mode, the MP5048

charges and discharges the TIMER pin nine

times using the same rates as the insertion delay.

After the ninth cycle, the MP5048 automatically

retries a start-up sequence (see Figure 12).

t

FAULT

VOUT

Retry Delay Time

TIMER

4V

2.4V

3.5µs Hold

7.5µs Hold

1

2

2µA

~500nA

200mV

9

Figure 12: MP5048 Auto-Retry

Current Limit at Start-Up

The MP5048 load current is limited by the

current limit reference input and the CS external

resistor. The CS voltage (VCS) is compared to the

current limit reference through an amplifier to

regulate the power FET gate voltage. This

prevents the Intelli-Fuse current from exceeding

the current limit defined by the reference.

The current limit reference voltage is set through

CLREF, which is clamped low internally during

soft start to control VOUT and allow it to ramp up

gradually. Once VOUT is close to VIN, the current

limit reference can be raised to the full current

limit set by the CLREF voltage. At this point, the

power FET gate is fully enhanced, and the e-fuse

is ready to deliver full power from the input.

To protect the MP5048 from overheating during

start-up, the current limit internal maximum

clamp

voltage

and

CS

limit

reference

configuration current change based on VIN and

VOUT (see Figure 13).