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MCP98244 Datasheet(PDF) 9 Page - Microchip Technology

Part # MCP98244
Description  DDR4 DIMM Temperature Sensor with EEPROM for SPD
PDF  52 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP98244 Datasheet(HTML) 9 Page - Microchip Technology

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 2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002327D-page 9
MCP98244
4.0
SERIAL COMMUNICATION
4.1
2-Wire Standard Mode I2C™
Protocol-Compatible Interface
The MCP98244 serial clock input (SCL) and the
bidirectional serial data line (SDA) form a 2-wire
bidirectional
Standard
mode
I2C-compatible
communication port (refer to the Input/Output Pin DC
Characteristics table and Serial Interface Timing Spec-
ifications table).
The following bus protocol has been defined:
TABLE 4-1:
MCP98244 SERIAL BUS
PROTOCOL DESCRIPTIONS
4.1.1
DATA TRANSFER
Data transfers are initiated by a Start condition
(START), followed by a 7-bit device address and a
read/write bit. An Acknowledge (ACK) from the client
confirms the reception of each byte. Each access must
be terminated by a Stop condition (STOP).
Repeated communication is initiated after tB-FREE.
This device does not support sequential register
read/write. Each register needs to be addressed using
the Register Pointer.
This device supports the Receive Protocol. The
register can be specified using the pointer for the initial
read. Each repeated read or receive begins with a Start
condition and address byte. The MCP98244 retains the
previously selected register. Therefore, they output
data from the previously-specified register (repeated
pointer specification is not necessary).
4.1.2
HOST/CLIENT
The bus is controlled by a host device (typically a
microcontroller) that controls the bus access and
generates the Start and Stop conditions. The
MCP98244 is a client device and does not control other
devices in the bus. Both host and client devices can
operate as either transmitter or receiver. However, the
host device determines which mode is activated.
4.1.3
START/STOP CONDITION
A high-to-low transition of the SDA line (while SCL is
high) is the Start condition. All data transfers must be
preceded by a Start condition from the host. A
low-to-high transition of the SDA line (while SCL is
high) signifies a Stop condition.
If a Start or Stop condition is introduced during data
transmission, the MCP98244 releases the bus. All data
transfers are ended by a Stop condition from the host.
4.1.4
ADDRESS BYTE
Following the Start condition, the host must transmit an
8-bit address byte to the MCP98244. The address for
the
MCP98244
Temperature
Sensor
is
‘0011,A2,A1,A0’ in binary, where the A2, A1 and A0
bits are set externally by connecting the corresponding
pins to VDD ‘1’ or GND ‘0’. The 7-bit address
transmitted in the serial bit stream must match the
selected address for the MCP98244 to respond with an
ACK. Bit 8 in the address byte is a read/write bit.
Setting this bit to ‘1’ commands a read operation, while
‘0’ commands a write operation (see Figure 4-1).
FIGURE 4-1:
Device Addressing.
4.1.5
DATA VALID
After the Start condition, each bit of data in
transmission needs to be settled for a time specified by
tSU-DATA before SCL toggles from low-to-high (see
Serial Interface Timing Specifications table).
Term
Description
Host
The device that controls the serial bus,
typically a microcontroller.
Client
The device addressed by the host,
such as the MCP98244.
Transmitter Device sending data to the bus.
Receiver
Device receiving data from the bus.
START
A unique signal from host to initiate
serial interface with a client.
STOP
A unique signal from the host to
terminate serial interface from a client.
Read/Write A read or write to the MCP98244
registers.
ACK
A receiver Acknowledges (ACK) the
reception of each byte by polling the
bus.
NAK
A receiver Not-Acknowledges (NAK) or
releases the bus to show End-of-Data
(EOD).
Busy
Communication is not possible
because the bus is in use.
Not Busy
The bus is in the idle state, both SDA
and SCL remain high.
Data Valid
SDA must remain stable before SCL
becomes high in order for a data bit to
be considered valid. During normal
data transfers, SDA only changes state
while SCL is low.
1 2 34 5 678 9
SCL
SDA
0 0
1 1 A2 A1 A0
Start
Address Byte
Client
Address
R/W
MCP98244 Response
Code
Address
A
C
K



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