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UPD17708 Datasheet(PDF) 44 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 44 Page - Renesas Technology Corp |
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44 / 358 page  µPD17704, 17705, 17707, 17708, 17709 42 Table 4-1. Data Memory Manipulation Instructions Function Instruction Operation Add ADD ADDC Subtract SUB SUBC Logic AND OR XOR Compare SKE SKGE SKLT SKNE Transfer MOV LD ST Judge SKT SKF 4.3 Data Memory Addressing Figure 4-3 shows address specification of the data memory. An address of the data memory is specified by a bank, row address, and column address. A row address and a column address are directly specified by a data memory manipulation instruction. However, a bank is specified by the contents of a bank register. For the details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG). Figure 4-3. Address Specification of Data Memory Data memory address Bank register Column address Row address Bank b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 Instruction operand |
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