UPD17708 datasheet(52/358 Pages) RENESAS

52 / 358 page

µPD17704, 17705, 17707, 17708, 17709

5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: memory pointer)

5.6.1 Configuration of index register and data memory row address pointer

Figure 5-6 shows the configuration of the index register and data memory row address pointer.

As shown in the figure, the index register consists of an index register (IX) made up of 11 bits (the low-order

3 bits (IXH) of system register address 7AH, and 7BH and 7CH (IXM, IXL)) and an index enable flag (IXE) at

the lowest bit position of 7FH (PSW).

The data memory row address pointer (memory pointer) consists of a data memory row address pointer (MP)

that is made up of 7 bits of the low-order 3 bits of 7AH (MPH) and 7BH (MPL), and a data memory row address

pointer enable flag (memory pointer enable flag: MPE) at the lowest bit position of 7AH (MPH).

In other words, the high-order 7 bits of the index register are shared with the data memory row address pointer

Figure 5-6. Configuration of Index Register and Data Memory Row Address Pointer

Address

Name

Symbol

Bit

Data

Clock stop

7AH

IXH

MPH

Retained

7BH

Index register (IX)

IXM

MPL

Retained

7CH

IXL

Retained

7EH

7FH

PSW

Memory pointer (MP)

Power-ON reset

WDT&SP reset

CE reset

Program status word

(PSWORD)

R: retained

UPD17708 Datasheet(PDF) 52 Page - Renesas Technology Corp