STE10A datasheet(52/82 Pages) STMICROELECTRONICS

52 / 82 page

Registers and descriptors description

STE10/100A

52/82

22~ 20

Transmit state. Reports the current transmission

state only, no interrupt will be generated.

000: stop

001: read descriptor

010: transmitting

011: FIFO fill, read the data from memory and

put into FIFO

100: reserved

101: reserved

110: suspended, unavailable transmit descriptor

or FIFO overflow

111: write descriptor

000

19~17

Receive state. Reports current receive state

only, no interrupt will be generated.

000: stop

001: read descriptor

010: check this packet and pre-fetch next

descriptor

011: wait for receiving data

100: suspended

101: write descriptor

110: flush the current FIFO

111: FIFO drain, move data from receiving FIFO

into memory

000

ANISS

Added normal interrupt status summary.

1: whenever any of the added normal interrupts

occur.

0RO/LH*

AAISS

Added abnormal interrupt status summary.

1: whenever any of the added abnormal

interrupts occur.

1RO/LH*

14~0

These bits are the same as the status register of

CSR5, and are accessible through either CSR5

or CSR16.

LH* = High Latching and cleared by writing 1

CSR17 (offset = 84h), ACSR7- Assistant CSR7 (Interrupt enable register 2)

TEIE

Transmit early interrupt enable

R/W

REIE

Receive early interrupt enable

R/W

XIE

Transceiver (XCVR) interrupt enable

R/W

TDIE

Transmit deferred interrupt enable

R/W

---

Reserved

PFRIE

PAUSE frame received interrupt enable

R/W

25~17

---

Reserved

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

STE10A Datasheet(PDF) 52 Page - STMicroelectronics

STE10A Datasheet(HTML) 52 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL