STE10A datasheet(67/82 Pages) STMICROELECTRONICS

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STE10/100A

Registers and descriptors description

67/82

First descriptor

Last descriptor

7TL

Packet too long (packet length > 1518 bytes). This bit is valid only in a

frame’s last descriptor.

6CS

Late collision. Set when collision is active after 64 bytes. This bit is valid only

in a frame’s last descriptor

5FT

Frame type. This bit is valid only in a frame’s last descriptor.

0: 802.3 type

1: Ethernet type

4RW

Receive watchdog (refer to CSR15, bit 4). This bit is valid only in a frame’s

last descriptor.

reserved

Default = 0

2DB

Dribble bit. This bit is valid only in a frame’s last descriptor

1: Packet length is not integer multiple of 8-bit

1: CRC error. This bit is valid only in a frame’s last descriptor

1: Overflow. This bit is valid only in a frame’s last descriptor

RDES1

31~26

---

Reserved

RER

Receive end of ring. Indicates this descriptor is last, return to base address

of descriptor

RCH

Second address chain

Used for chain structure, indicating the buffer 2 address is the next descriptor

address. Ring mode takes precedence over chained mode

23~22

---

Reserved

21~11

RBS2

Buffer 2 size (DW boundary)

10~ 0

RBS1

Buffer 1 size (DW boundary)

RDES2

31~0

RBA1

Receive buffer address 1. This buffer address should be double word

aligned.

RDES3

31~0

RBA2

Receive buffer address 2. This buffer address should be double word

aligned.

Table 12.

Receive descriptor description (continued)

Bit#

Name

Description

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