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UPD784021 Datasheet(PDF) 13 Page - Renesas Technology Corp |
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UPD784021 Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 92 page  11 m m m m mPD784020, 784021 5. BLOCK DIAGRAM Remark The internal ROM or RAM capacity differs for each product. NMI INTP3 TO0 TO1 INTP0 INTP1 INTP2/CI TO2 TO3 P00-P03 P04-P07 PWM0 PWM1 ANO0 ANO1 AVREF2 AVREF3 INTP5 ANI0-ANI7 TxD/SO1 ASCK/SCK1 RxD/SI1 ASCK2/SCK2 SCK0 SO0/SB0 SI0 A8-A15 P00-P07 P20-P27 P10-P17 P30-P37 P60, P67 P70-P77 ASTB REFRQ/HLDAK WR WAIT/HLDRQ AD0-AD7 RD A16-A19 P60-P63 X1 X2 RESET TEST VDD VSS AVDD AVREF1 AVSS UART/IOE2 Baud-rate generator UART/IOE1 Clocked serial interface Bus interface Port 0 Port 1 Port 2 Port 3 Port 6 Port 7 System control Programmable interrupt controller Timer/counter 0 Timer/counter 1 Timer/counter 2 Timer 3 Real-time output port PWM D /A converter A /D converter INTP0-INTP5 (16 bits) (16 bits) (16 bits) (16 bits) 78K /IV CPU core Watchdog timer Baud-rate generator TxD2/SO2 RxD2/SI2 RAM |
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