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7-Bit Slave Address

R/

W

8-Bit Register Address (N)

A

8-Bit Register Data For

Address (N)

Start

Stop

SDA

SCL

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

A

7

6

5

4

3

2

1

0

8-Bit Register Data For

Address (N)

7

6

5

4

3

2

1

0

A

A

T0035-01

SINGLE- AND MULTIPLE-BYTE TRANSFERS

TAS5086

SLES131A – FEBRRUARY 2005 – REVISED MAY 2006

supports both 100-kb/s and 400-kb/s data transfer rates for single- and multiple-byte write and read operations.

The control interface is used to program the registers of the device and to read device status.

(400 kHz maximum).

system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte

(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions.

A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit

transitions must occur within the low time of the clock period. These conditions are shown in Figure 14. The

master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then wait for an acknowledge condition. The TAS5086 holds SDA low during acknowledge clock

period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.

Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share

the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used

for the SDA and SCL signals to set the HIGH level for the bus.

An unlimited number of bytes can be transmitted between start and stop conditions. When the last word

transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown

in Figure 14.

The 7-bit address for the TAS5086 is 0011011.

The serial control interface supports both single-byte and multiple-byte read/write operations for status registers

and the general control registers associated with the PWM. However, for the DAP data processing registers, the

serial control interface supports only multiple-byte (4-byte) read/write operations.

During multiple-byte read operations, the TAS5086 responds with data, a byte at a time, starting at the

subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular

subaddress does not contain 32 bits, the unused bits are read as logic 0.

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