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TAS5086DBT Datasheet(PDF) 16 Page - Texas Instruments

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Part # TAS5086DBT
Description  PurePath Digital TM AUDIO SIX-CHANNEL PWM PROCESSOR
PDF  41 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5086DBT Datasheet(HTML) 16 Page - Texas Instruments

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22
SCLK
24 Clks
LRCLK
Left Channel
24-Bit Mode
1
19
18
20-Bit Mode
16-Bit Mode
15
14
MSB
LSB
SCLK
24 Clks
Right Channel
MSB
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
T0092-02
4
5
9
8
17
16
1
4
5
13
12
1
9
8
0
0
0
21
17
13
23
22
1
19
18
15
14
4
5
9
8
17
16
1
4
5
13
12
1
9
8
0
0
0
21
17
13
LSB
Right-Justified
TAS5086
SLES131A – FEBRRUARY 2005 – REVISED MAY 2006
SERIAL INTERFACE CONTROL AND TIMING (continued)
Figure 11. Left-Justified 48-fS Format
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock
running at 64- fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode, the LSB of data always is clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5086 masks
unused leading data bit positions.
16
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