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TAS5086DBT Datasheet(PDF) 22 Page - Texas Instruments |
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TAS5086DBT Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 41 page  www.ti.com CLOCK CONTROL REGISTER (0x00) TAS5086 SLES131A – FEBRRUARY 2005 – REVISED MAY 2006 SERIAL CONTROL INTERFACE REGISTER SUMMARY (continued) NO. OF SUBADDRESS REGISTER NAME CONTENTS INITIALIZATION VALUE BYTES 0x08 Channel 1 vol 1 Description shown in subsequent section 30 (0 dB) 0x09 Channel 2 vol 1 Description shown in subsequent section 30 (0 dB) 0x0A Channel 3 vol 1 Description shown in subsequent section 30 (0 dB) 0x0B Channel 4 vol 1 Description shown in subsequent section 30 (0 dB) 0x0C Channel 5 vol 1 Description shown in subsequent section 30 (0 dB) 0x0D Channel 6 vol 1 Description shown in subsequent section 30 (0 dB) 0x0E Volume control register 1 Description shown in subsequent section B1 0x0F RESERVED(1) 0x10 Modulation limit register 1 Description shown in subsequent section 02 0x11–0x17 RESERVED(1) 0x18 PWM start register 1 Description shown in subsequent section 3F 0x19 Surround register 1 Description shown in subsequent section 00 0x1A Split cap charge period register 1 Description shown in subsequent section 18 0x1B OSC_TRIM 1 Oscillator Trim Register 82 0x1C BKNDERR register 1 BKNDErr Register 05 0x1D–0x1F RESERVED(1) 0x20 Input MUX register 4 Description shown in subsequent section 0x00, 0x01, 0x23, 0x45 0x21 Downmix input MUX register 4 Description shown in subsequent section 0x00, 0x00, 0x00, 0x3F 0x22 AM tuned frequency 4 Description shown in subsequent section 0x00, 0x00, 0x00, 0x00 0x23 ch6_bq[1] 20 b0[25:24] b0[(23:16], b0[15:8], b0[7:0] 0x00, 0x80, 0x00, 0x00 b1[25:24] b1[23:16], b1[15:8], b1[7:0] 0x00, 0x00, 0x00, 0x00 b2[25:24] b2[23:16], b2[15:8], b2[7:0] 0x00, 0x00, 0x00, 0x00 a1[25:24] a1[23:16], a1[15:8], a1[7:0] 0x00, 0x00, 0x00, 0x00 a2[25:24] a2[23:16], a2[15:8], a2[7:0] 0x00, 0x00, 0x00, 0x00 0x24 ch6_bq[2] 20 b0[25:24] b0[23:16], b0[15:8], b0[7:0] 0x00, 0x80, 0x00, 0x00 b1[25:24] b1[23:16], b1[15:8], b1[7:0] 0x00, 0x00, 0x00, 0x00 b2[25:24] b2[23:16], b2[15:8], b2[7:0] 0x00, 0x00, 0x00, 0x00 a1[25:24] a1[23:16], a1[15:8], a1[7:0] 0x00, 0x00, 0x00, 0x00 a2[25:24] a2[23:16], a2[15:8], a2[7:0] 0x00, 0x00, 0x00, 0x00 0x25 PWM MUX register Shown in Subsection section 0x00, 0x32, 0x45, 0x10 0x26 1/G register 4 x[25:24] x[23:16], x[15:8], x[7:0] 0x00, 0x80, 0x00, 0x00 0x27 RESERVED(1) 0x28 Scale register 4 x[25:24] x[23:16], x[15:8], x[7:0] 0x00, 0x80, 0x00, 0x00 0x29–0xFD RESERVED(1) 0xFE Repeat subaddress 4+4N 0x00, 0x00, 0x00, 0x00 0xFF RESERVED(1) (1) Reserved registers should not be accessed. In the manual mode, the clock control register provides a way for the system microprocessor to update the data and clock rates, based on the sample rate and associated clock frequencies. In the autodetect mode, the clocks are determined automatically by the TAS5086. In this case, the clock control register contains the autodetected clock status as automatically detected. Bits D7–D5 selects the sample rate. Bits D4–D2 select the MCLK frequency. Bit D1 selects the bit clock (SCLK) frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated, a 1 must be written to D1 to inform the TAS5086 that the written clocks are valid. 22 Submit Documentation Feedback |
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