TAS5086DBT datasheet(24/41 Pages) TI

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ERROR STATUS REGISTER (0x02)

SYSTEM CONTROL REGISTER 1 (0x03)

TAS5086

SLES131A – FEBRRUARY 2005 – REVISED MAY 2006

Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must

clear the register (write zeroes) and then read them to determine if there are any persistent errors.

Table 3. Error Status Register (0x02)

FUNCTION

–

PLL auto lock error

–

SCLK error

–

LRCLK error

–

Frame slip

–

No errors

System control register 1 has several functions:

Bit D7: If 0, the dc-blocking filter for each channel is disabled.

If 1, the dc-blocking filter (–3-dB cutoff < 1 Hz) for each channel is enabled (default).

Bit D6: Not used

Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery.

If 1, use hard unmute on recovery from clock error (default). This is a fast recovery.

Bit D4: If 0, the downmix is output on SDOUT as I2S signal (default).

If 1, SDIN4 is output on SDOUT as I2S signal.

Bit D3: If 0, clock autodetect is enabled (default).

If 1, clock autodetect is disabled.

Bit D2: If 0, soft start is enabled (default).

If 1, soft start is disabled.

Bit D1-D2: Select de-emphasis

Table 4. System Control Register 1 (0x03)

FUNCTION

–

PWM high-pass (dc blocking) disabled

–

PWM high-pass (dc blocking) enabled

–

Soft unmute on recovery from clock error

–

Hard unmute on recovery from clock error

–

Output downmix on SDOUT

–

Output SDIN4 mix on SDOUT

–

Enable clock autodetect

–

Disable clock autodetect

–

Enable soft start

–

Disable soft start

–

No de-emphasis

–

De-emphasis for fS = 32 kHz

–

De-emphasis for fS = 44.1 kHz

–

De-emphasis for fS = 48 kHz

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