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AM69 Datasheet(PDF) 162 Page - Texas Instruments |
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AM69 Datasheet(HTML) 162 Page - Texas Instruments |
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162 / 300 page  J7VCL_ELCH_05 T0 T1 T2 T3 T4 Valid Configuration T0 T1 T2 T3 VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU (2) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDA_3P3_USB (4) (2) (5) (VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU, VDDA_POR_WKUP, VDDA_WKUP) (6) VDD MCU VDD MCU WAKE VDDAR MCU _ , _ _ 1, _ (9) VDD CORE VDD WAKE VDDA P SERDES _ , _ 0, _0 8_ , _0 8_ _ , _0 8_ VDDA P SERDES C VDDA P USB VDDAR CORE VDDAR CPU _ , _ MCU_PORz (10)(11) PORz (10)(11) OSC1_XI, OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) WKUP_OSC0_XI, WKUP_OSC0_XO (optional) VDDS DDR BIAS VDDS DDR VDDS DDR C _ _ , _ , _ _ (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU) (3) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5, VDDSHV6) (3) VDDS_MMC0 (VDDA_OSC1, VDDA_PLLGRP8, VDDA_PLLGRP6, VDDA_PLLGRP4, VDDA_PLLGRP0, VDDA_TEMP1, VDDA_TEMP0) (7) VDD_CPU T4 (VDDA_1P8_SERDES, VDDA_1P8_USB) (7) ( _0 8_ _ , _0 8_ _ 0) VDDA P PLL DDR VDDA P DLL MMC (8) MCU_BOOTMODE[9:0], BOOTMODE[7:0] (10) Active Active Entry into MCU only MCU only Exit from MCU only T Δ1 Figure 7-7. Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State Entry into DDR Retention state is accomplished by executing a power down sequence except for the 4 DDR domains that remain energized. Exit from DDR Retention state is accomplished by executing a power up sequence with the 3 DDR domains remaining energized throughout the sequence. AM69A, AM69 SPRSP92A – FEBRUARY 2023 – REVISED AUGUST 2023 www.ti.com 162 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AM69A AM69 |
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