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7.10.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,

see the corresponding sections within Signal Descriptions and Detailed Description.

Table 7-5. System Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

7.10.3.1 Reset Timing

The tables and figures provided in this section define the timing requirements and switching characteristics for

reset related signals.

Table 7-6. MCU_PORz Timing Requirements

see Figure 7-10

NO.

MIN

TYP

MAX UNIT

RST1

th(MCUD_SUPPLIES_VALID - MCU_PORz)

Hold time, MCU_PORz active (low) at Power-

up after all MCU DOMAIN supplies valid (using

external crystal)

N +

1200(2)

9500000

RST2

Hold time, MCU_PORz active (low) at Power-

up after all MCU DOMAIN supplies(1) valid and

external clock stable (using external LVCMOS

oscillator)

1200

RST3 tw(MCU_PORzL)

Pulse Width minimum, MCU_PORz low after

Power-up (without removal of Power or system

reference clock MCU_OSC0_XI/XO)

1200

(1)

For the definition of the MCU DOMAIN supplies, see the Section 7.10.2.2, Combined MCU and Main Domains Poewr-Up Sequencing.

(2)

N = oscillator start-up time

MCU_PORz

RST1

RST3

MCU_OSC0_XI,

MCU_OSC0_XO

RST2

MCU DOMAIN

SUPPLIES VALID

Figure 7-10. MCU_PORz Timing Requirements

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AM69A, AM69

SPRSP92A – FEBRUARY 2023 – REVISED AUGUST 2023

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