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AM69 Datasheet(PDF) 113 Page - Texas Instruments |
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AM69 Datasheet(HTML) 113 Page - Texas Instruments |
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113 / 300 page  Table 6-88. PCIE Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] PCIE3_TXN0 O SERDES_PCIE Differential Transmit Data (negative) AV9 PCIE3_TXN1 O SERDES_PCIE Differential Transmit Data (negative) AV12 PCIE3_TXP0 O SERDES_PCIE Differential Transmit Data (positive) AV10 PCIE3_TXP1 O SERDES_PCIE Differential Transmit Data (positive) AV13 PCIE_REFCLK0_N_OUT O SERDES_PCIE Reference Clock Negative AP4 PCIE_REFCLK0_P_OUT O SERDES_PCIE Reference Clock Positive AP5 PCIE_REFCLK1_N_OUT O SERDES_PCIE Reference Clock Out Negative AN8 PCIE_REFCLK1_P_OUT O SERDES_PCIE Reference Clock Out Positive AN9 PCIE_REFCLK2_N_OUT O SERDES_PCIE Reference Clock Out Negative AN5 PCIE_REFCLK2_P_OUT O SERDES_PCIE Reference Clock Out Positive AN6 PCIE_REFCLK3_N_OUT O SERDES_PCIE Reference Clock Out Negative AP7 PCIE_REFCLK3_P_OUT O SERDES_PCIE Reference Clock Out Positive AP8 6.3.20 SERDES 6.3.20.1 MAIN Domain Table 6-89. SERDES0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES0_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AU9 SERDES0_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AU8 SERDES0_REXT (1) I External Calibration Resistor AN11 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. Table 6-90. SERDES1 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES1_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV3 SERDES1_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV4 SERDES1_REXT (1) I External Calibration Resistor AL9 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. Table 6-91. SERDES2 Signal Descriptions SIGNAL NAME [1] ((2)) PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES2_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV21 SERDES2_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV22 SERDES2_REXT (1) IO External Calibration Resistor AL20 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) DDRSS2, DDRSS3, and SERDES2 are not available on the 27mm package variant of this SoC. DDRSS2/DDRSS3/SERDES2 should be avoided if software compatibility is desired with systems that use the 27mm package. Table 6-92. SERDES4 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES4_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV16 SERDES4_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV15 SERDES4_REXT (1) IO External Calibration Resistor AM19 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. www.ti.com AM69A, AM69 SPRSP92A – FEBRUARY 2023 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: AM69A AM69 |
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