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DFE252012C Datasheet(PDF) 35 Page - Texas Instruments |
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DFE252012C Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 63 page ![]() 9.6.9 Status Register [reset = 0x05] Memory location: 0x05 Figure 9-18. Status Register 7 6 5 4 3 2 1 0 TSD HOTDIE DCDCMODE OPMODE ILIMPT ILIMBST FAULT PGOOD R R R R R R R R Stored in E2 N N N N N N N N Table 9-8. Status Register Field Descriptions Bit Field Type Reset Description 7 TSD R 0 Thermal shutdown status bit. 0: Normal operation. 1: Thermal shutdown tripped. This flag is reset after readout. 6 HOTDIE R 0 Instantaneous die temperature bit. 0: TJ < 115°C. 1: TJ > 115°C. 5 DCDCMODE R 0 DC/DC mode of operation status bit. 1: Device operates in PFM mode. 0: Device operates in PWM mode. 4 OPMODE R 0 Device mode of operation status bit. 0: Device operates in pass-through mode. 1: Device operates in dc/dc mode. 3 ILIMPT R 0 Current limit status bit (pass-through mode). 0: Normal operation. 1: Indicates that the bypass FET current limit has triggered. This flag is reset after readout. 2 ILIMBST R 0 Current limit status bit (dc/dc boost mode). 0: Normal operation. 1: Indicates that the average input current limit has triggered for 1.5ms in dc/dc boost mode. This flag is reset after readout. 1 FAULT R 0 FAULT status bit. 0: Normal operation. 1: Indicates that a fault condition has occurred. This flag is reset after readout. 0 PGOOD R 0 Power Good status bit. 0: Indicates the output voltage is out of regulation. 1: Indicates the output voltage is within its nominal range. This bit is set if the converter is forced in pass-through mode. www.ti.com TPS61280D, TPS61281D, TPS61282D,, TPS61280E SLVSEA0B – JANUARY 2018 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E |
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