DFE252012C datasheet(4/63 Pages) TI1

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7 Pin Configuration and Functions

Not to scale

GPIO

VIN

VSEL

SCL

VOUT

nBYP

SDA

AGND

PGND

Figure 7-1. TPS61280D/E YFF Package 16-Bump

DSBGA Top View

Not to scale

AGND

PGND

nBYP

SDA

VSEL

SCL

VOUT

GPIO

VIN

Figure 7-2. TPS61280D/E YFF Package 16-Bump

DSBGA Bottom View

Table 7-1. Pin Functions, TPS61280D/E

I/O

DESCRIPTION

NAME

NO.

VIN

A3, A4

Power supply input.

VOUT

B3, B4

Boost converter output.

This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default

values. This input must not be left floating and must be terminated.

EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the

logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be

regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current

consumption is reduced to a few µA. For more details, refer to Table 9-2.

EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For more

details, refer to Table 9-2.

GPIO

I/O

This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/ FAULT )

pin. For TPS61280D, default configuration is RST/ FAULT input/output. For TPS61280E, default configuration is

mode selection input. The input must not be left floating and must be terminated.

Manual Reset Input: Drive RST/ FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a

falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output

followed by a start-up phase.

Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output

voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling

edge-triggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state.

Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at

high-load currents and in pulse frequency modulation mode (PFM) at light load currents.

Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced.

VSEL

VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left

floating and must be terminated.

nBYP

A logic low level on the BYP input forces the device in pass-through mode. This pin must not be left floating and must

be terminated.

SCL

Serial interface clock line. This pin must not be left floating and must be terminated.

SDA

I/O

Serial interface address/data line. This pin must not be left floating and must be terminated.

C3, C4

I/O

Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.

PGND

D2, D3, D4

Power ground pin.

AGND

Analog ground pin. This is the signal ground reference for the IC.

TPS61280D, TPS61281D, TPS61282D,, TPS61280E

SLVSEA0B – JANUARY 2018 – REVISED JUNE 2023

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Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E

DFE252012C Datasheet(PDF) 4 Page - Texas Instruments

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