ES9080 datasheet(141/146 Pages) ESS

141 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

141

ES9080 Product Datasheet

w 0x90 143 0x1A; //Set DRE digital gain to CH2/4/6/8 to 16.37dB to match the Analog

attenuate amount when DRE turns on

w 0x90 144 0xF1; //Set DRE ON threshold to -48dB

w 0x90 145 0x0C; //Set DRE ON threshold to -48dB

w 0x90 146 0x84; //Set DRE OFF threshold to -28dB

w 0x90 147 0x81; //Set DRE OFF threshold to -28dB

w 0x90 148 0x8F; //Set DRE decay rate (time it takes to automatically engage DRE if the

signal drops below the DRE ON threshold

//Enable Audio

w 0x90 92 0x10;

//Toggle DAC clock Resync to line up all the clocks in the DAC core for

best analog performance

w 0x90 92 0x0F;

//Toggle DAC clock Resync to line up all the clocks in the DAC core for

best analog performance

w 0x90 92 0x00;

//Toggle DAC clock Resync to line up all the clocks in the DAC core for

best analog performance

w 0x90 0 0x02;

//Turn on the AMP

(This runs a state machine to gracefully turn on the

DAC's)

TDM Slave

//Initialize Slave Mode TDM with 8 channels, MCLK = 49.152MHz, fs = 48kHz, DRE enabled,

automute enabled

w 0x98 192 0x03; //Set GPIO1 (MCLK) pad to input mode, Invert CLKHV phase for better DNR

w 0x98 193 0xC3; //Set PLL Bypass, Remove 10k DVDD shunt to ground, set PLL input to MCLK,

enable the PLL clock inputs

w 0x98 202 0x40; //Set PLL Parameters

w 1 0xFF;

//Enable Interpolation and modulator clocks for all 8 channels

w 2 0x01;

//Enable the TDM decoder

//Sample Rate register (MCLK/fs ratio)

//w 3 0x00;

//MCLK = 128FS Eg, 49.152MHz/384kHz

//w 3 0x01;

//MCLK = 256FS Eg, 49.152MHz/192kHz

//w 3 0x03;

//MCLK = 512FS Eg, 49.152MHz/96kHz

w 3 0x07;

//MCLK = 1024FS Eg, 49.152MHz/48kHz

w 5 0xFF;

//Enable all 8 channels Analog section.

w 6 0x1F;

//Set the PNEG charge pump clock frequency to 705.6kHz or 768kHz (depending on

MCLK being 22.5792MHz or 24.576MHz)

w 7 0xBB;

//Setup automated delay sequence for analog section quietest pop

w 51 0x80;

//Force a PLL_LOCKL signal from analog since it it bypassed to prevent muting

the DAC automatically

//TDM Registers

ES9080 Datasheet(PDF) 141 Page - ESS Technology,Inc

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