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ES9080 Datasheet(PDF) 145 Page - ESS Technology,Inc |
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ES9080 Datasheet(HTML) 145 Page - ESS Technology,Inc |
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145 / 146 page  CONFIDENTIAL ADVANCE INFORMATION 0.4.3 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 145 ES9080 Product Datasheet • Added clock distribution section 0.4 August 25, 2021 • Added TDM timing diagram • Updated names and descriptions for registers 136 and 62 • Added THD compression calculation • Changed equations in registers 102-104 • Added soft mute, automute, and volume control sections • Added note on reserved registers to register listing section • Major formatting updates • Unreserved register 49[5:4], 8 • Updated Digital Signal Path section • Added de-emphasis filter section • Added DRE section • Added note on SPDIF_SEL_GPIO# registers in S/PDIF encoders section • Added Clock Distribution tables 0.4.1 October 6th, 2021 • Added PLL configurations Table • Register 154 updated for clarity, it is a digital gain • Added w/o DRE DNR performance number • Corrected Register Map table • Added note regarding DSD for Register 82[5] ENABLE_WS_MONITOR • Updated Registers 129, 203, 140-143 descriptions • Unreserved Register 80[5:0] TDM_VALID_PULSE_LEN • Added Addendum for example setup register listings • Updated some descriptions in Synchronous Slave Interface registers • Reserved Register 77[6], default is required • Corrected Register 144-147 description values • Updated Digital Signal Path diagram with DSD/DoP & SPDIF path 0.4.2 October 26th, 2021 • Updated DNR performance values w/o DRE, added 4ch[SE], stereo[Diff], mono 0.4.3 April 7th, 2022 • Removed incorrect Power Up sequence, updated Power Up and Down sequences • Updated filter characteristics with additional passband • Removed Automute reference to DSD as Automute is only available for PCM • Updated Register 31 Bit 4 Default state • Corrected Register 49 Bit configuration • Unreserved Register 51[7] FORCE_PLL_LOCK • Updated Registers 59-58, 61-60 Defaults • Updated Registers 84-91[3:0] Description 4 bits for 16 slots • Updated Register 104 Default state in description • Added Register 225 (CHIP_ID) as 8’h67 • Added Note on DRE section • Updated Registers 248-247 Bits width • Updated Registers 68-76 PWM descriptions for valid ranges • Updated Reference schematic for readability • Added Note to Register 51 FORCE_PLL_LOCK |
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