MAX77720 datasheet(13/52 Pages) AD

13 / 52 page

Wide Output-Voltage Range, Dual-

Polarity PMIC

MAX77720

www.analog.com

Analog Devices | 13

Note 2: Output accuracy does not include load, line, or ripple.

Note 3: This is a static measurement. The actual peak current limit depends upon VIN and the inductor due to propagation delays.

Note 4: Measured opened loop. Propagation delays not included.

Note 5: Design guidance only. Not production tested.

Note 6:

fSCL must meet the minimum clock low time plus the rise/fall times.

Note 7:

The maximum tHD_DATA has to be met only if the device does not stretch the low period (tLOW) of the SCL

signal.

Note 8:

This device internally provides a hold time of at least 100ns for the SDA signal (referred to the minimum VIH of

the SCL signal) to bridge the undefined region of the falling edge of SCL.

Typical Operating Characteristics

VIN = 3.6V, VOUTIBB = -18V, VOUTBST = 10V, limits are 100% production tested at TJ = +25°C. Limits over the operating

temperature range (TJ = -40°C to +125°C) and relevant voltage range are guaranteed by design and characterization,

unless otherwise noted.

MAX77720 Datasheet(PDF) 13 Page - Analog Devices