MAX77720 datasheet(21/52 Pages) AD

21 / 52 page

Wide Output-Voltage Range, Dual-

Polarity PMIC

MAX77720

www.analog.com

Analog Devices | 21

POWER-UP DELAY

RESOURCE ON

POWER-DOWN DELAY

SHUTDOWN

VOUTBST/ t

VIBB/ t

tD_BST_UP

BIAS ON

tD_IBB_UP

tD_BST_DN

tD_IBB_DN

EN PIN

VOUT_IBB

VOUT_BST

tSBIAS_EN

BIAS EN

Figure 3. Start-Up Programmable Timing Diagram (Includes EN_Bias Timing with CNFG_GLBL.EN_BIAS = 0)

Soft-Start

The soft-start feature of the device limits inrush current during startup, which is achieved by limiting the slew rate of the

output voltage during startup (dV/dTSS). The MAX77720 soft-start begins when the EN pin is pulled high above VIH and

after the programmed delay for each individual regulator.

The output-voltage ramp rate for the boost regulator is a fixed 7mV/μs. The output-voltage ramp rate for the inverting

buck-boost regulator is dependent on the soft-start current limit setting, input voltage, and output voltage. See the

Electrical Characteristics for typical soft-start ramp rates for the selected settings. The two selectable soft-start current

limits allow for trading power-up time for minimum battery transient impact and should be changed for certain applications.

Shutdown

When the EN pin is pulled low (VEN < VEN_IL), the MAX77720 goes into the shutdown state. While in the shutdown state,

both regulators are not switching but are still programmable through I2C. See Figure 7 and Table 4 for details. The current

consumed in this mode is 235μA if the main bias is on with no regulators enabled.

nERR Error Pin

The error pin (nERR) is an active-low, digital input. When this pin receives a falling edge, the STAT_GLBL.ERR_PIN_S

asserts high and both the boost and the inverting buck-boost converters stop regulating. If the active discharge is disabled,

both regulators remain in a high-Z state, and the rate of discharge depends on the output load condition. To re-enable

the regulators, write a 0 to the CNFG_GLBL.FORCE_DIS bitfield through I2C. Once I2C clears it, both the boost and the

inverting buck-boost converters resume regulation again after the programmed timing startup delay with the programmed

soft-start enabled at any voltage.

Table 2 gives a summary of certain states while Figure 4 displays the output voltages with respect to the nERR pin if the

active discharge is disabled.

Table 2. Error Pin Summary

nERR

ERROR PIN STATUS

(STAT_GLBL.ERR_PIN_S)

FORCE DISABLE BIT

(CFNG_GLBL.FORCE_DIS)

INVERTING BUCK-BOOST

BOOST

High to

Low

High-Z

Low to

High

Keep 1 until I2C clears the

error by writing to a 0

Keep high-Z until I2C clears the

error

Keep high-Z until I2C

clears the error

MAX77720 Datasheet(PDF) 21 Page - Analog Devices

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