MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004

6

POST OFFICE BOX 655303

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External reset

Watchdog

Flash Memory

WDTIFG

KEYV

(see Note 1)

Reset

0FFFEh

15, highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

ACCVIFG

(see Notes 1 & 4)

(non)-maskable,

(non)-maskable,

(non)-maskable

0FFFCh

14

0FFFAh

13

0FFF8h

12

Comparator_A

CAIFG

maskable

0FFF6h

11

Watchdog Timer

WDTIFG

maskable

0FFF4h

10

Timer_A3

TACCR0 CCIFG (see Note 2)

maskable

0FFF2h

9

Timer_A3

TACCR1 CCIFG.

TACCR2 CCIFG

TAIFG (see Notes 1 & 2)

maskable

0FFF0h

8

0FFEEh

7

0FFECh

6

0FFEAh

5

0FFE8h

4

I/O Port P2

(eight flags; see Note 3)

P2IFG.0 to P2IFG.7

(see Notes 1 & 2)

maskable

0FFE6h

3

I/O Port P1

(eight flags)

P1IFG.0 to P1IFG.7

(see Notes 1 & 2)

maskable

0FFE4h

2

0FFE2h

1

0FFE0h

0, lowest

NOTES:

1. Multiple source flags

2. Interrupt flags are located in the module

3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) implemented on the ’C11x1 and ’F11x1A devices.

4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.