MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004

16

POST OFFICE BOX 655303

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs − Ports P1 and P2; (P1.0 to P1.7, P2.0 to P2.5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level output voltage

I(OHmax) = −1.5 mA

VCC = 2.2 V

See Note 1

VCC−0.25

VCC

VOH

High-level output voltage

Port 1 and Port 2 (C11x1)

I(OHmax) = −6 mA

VCC = 2.2 V

See Note 2

VCC−0.6

VCC

V

VOH

Port 1 and Port 2 (C11x1)

Port 1 (F11x1A)

I(OHmax) = −1.5 mA

VCC = 3 V

See Note 1

VCC−0.25

VCC

V

Port 1 (F11x1A)

I(OHmax) = −6 mA

VCC = 3 V

See Note 2

VCC−0.6

VCC

I(OHmax) = −1 mA

VCC = 2.2 V

See Note 3

VCC−0.25

VCC

VOH

High-level output voltage

I(OHmax) = −3.4 mA

VCC = 2.2 V

See Note 3

VCC−0.6

VCC

V

VOH

High-level output voltage

Port 2 (F11x1A)

I(OHmax) = −1 mA

VCC = 3 V

See Note 3

VCC−0.25

VCC

V

Port 2 (F11x1A)

I(OHmax) = −3.4 mA

VCC = 3 V

See Note 3

VCC−0.6

VCC

Low-level output voltage

I(OLmax) = 1.5 mA

VCC = 2.2 V

See Note 1

VSS

VSS+0.25

VOL

Low-level output voltage

Port 1 and Port 2 (C11x1,

I(OLmax) = 6 mA

VCC = 2.2 V

See Note 2

VSS

VSS+0.6

V

VOL

Port 1 and Port 2 (C11x1,

F11x1A)

I(OLmax) = 1.5 mA

VCC = 3 V

See Note 1

VSS

VSS+0.25

V

F11x1A)

I(OLmax) = 6 mA

VCC = 3 V

See Note 2

VSS

VSS+0.6

NOTES:

1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage

drop specified.

2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage

drop specified.

3. One output loaded at a time.

output frequency

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fP20

P2.0/ACLK, CL = 20 pF

2.2 V/3 V

fSystem

fTAx

Output frequency

TA0, TA1, TA2, CL = 20 pF

Internal clock source, SMCLK signal applied (see Note 1)

2.2 V/3 V

dc

fSystem

MHz

fSMCLK = fLFXT1 = fXT1

40%

60%

P1.4/SMCLK,

fSMCLK = fLFXT1 = fLF

2.2 V/3 V

35%

65%

P1.4/SMCLK,

CL = 20 pF

fSMCLK = fLFXT1/n

2.2 V/3 V

50%−

15 ns

50%

50%+

15 ns

tXdc

Duty cycle of O/P

frequency

fSMCLK = fDCOCLK

2.2 V/3 V

50%−

15 ns

50%

50%+

15 ns

frequency

P2.0/ACLK,

fP20 = fLFXT1 = fXT1

40%

60%

P2.0/ACLK,

CL = 20 pF

fP20 = fLFXT1 = fLF

2.2 V/3 V

30%

70%

CL = 20 pF

fP20 = fLFXT1/n

2.2 V/3 V

50%

tTAdc

TA0, TA1, TA2, CL = 20 pF, duty cycle = 50%

2.2 V/3 V

0

±50

ns

NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.