8.6 Register Maps

8.6.1 CDCDB803 Registers

Table 8-4 lists the CDCDB803 registers. All register locations not listed in Table 8-4 should be considered as

reserved locations and the register contents should not be modified.

Table 8-4. CDCDB803 Registers

Address

Acronym

Register Name

Section

0h

RCR1

Reserved Control Register 1

Go

1h

OECR1

Output Enable Control 1

Go

2h

OECR2

Output Enable Control 2

Go

3h

OERDBK

Output Enable# Pin Read Back

Go

4h

RCR2

Reserved Control Register 2

Go

5h

VDRREVID

Vendor/Revision Identification

Go

6h

DEVID

Device Identification

Go

7h

BTRDCNT

Byte Read Count Control

Go

8h

OUTSET

Output Setting Control

Go

4Ch

CAPTRIM

Slew Rate Capacitor Cluster 1 & 2

Go

Complex bit access types are encoded to fit into small table cells. Table 8-5 shows the codes that are used for

access types in this section.

Table 8-5. CDCDB803 Access Type Codes

Access Type

Code

Description

Read Type

R

R

Read

Write Type

W

W

Write

Reset or Default Value

-n

Value after reset or the default

value

8.6.1.1 RCR1 Register (Address = 0h) [reset = 47h]

RCR1 is shown in Table 8-6.

Return to the Summary Table.

The RCR1 register contains reserved bits.

Table 8-6. RCR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R

4h

Reserved.

3-0

Reserved

R/W

7h

Writing to these bits will not affect the functionality of the device.

8.6.1.2 OECR1 Register (Address = 1h) [reset = FFh]

OECR1 is shown in OECR1 Register Field Descriptions.

Return to the Summary Table.

The OECR1 register contains bits that enable or disable individual output clock channels [5:0].

CDCDB803

SNAS820A – AUGUST 2021 – REVISED MAY 2022

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