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CDCDB803 Datasheet(PDF) 4 Page - Texas Instruments

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Part # CDCDB803
Description  CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6
PDF  34 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCDB803 Datasheet(HTML) 4 Page - Texas Instruments

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Table 5-1. Pin Functions (continued)
PIN
TYPE(2)
DESCRIPTION
NAME
NO.
CK2_P
21
O
LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK2_N
22
O
CK3_P
25
O
LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK3_N
26
O
CK4_P
28
O
LP-HCSL differential clock output of channel 4. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK4_N
29
O
CK5_P
32
O
LP-HCSL differential clock output of channel 5. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK5_N
33
O
CK6_P
35
O
LP-HCSL differential clock output of channel 6. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK6_N
36
O
CK7_P
39
O
LP-HCSL differential clock output of channel 7. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK7_N
40
O
MANAGEMENT AND CONTROL (1)
CKPWRGD_PD#
1
I, S, PD
Clock Power Good and Power Down multi-function input pin with internal 180-kΩ
pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can
be left no connect. After PWRGD has been asserted high for the first time, the pin
becomes a PD# pin and it controls power-down mode:
LOW: Power-down mode, all output channels tri-stated.
HIGH: Normal operation mode.
OE0#
12
I, S, PD
Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 0.
HIGH: disable output channel 0.
OE1#
18
I, S, PD
Output Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 1.
HIGH: disable output channel 1.
OE2#
23
I, S, PD
Output Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 2.
HIGH: disable output channel 2.
OE3#
24
I, S, PD
Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 3.
HIGH: disable output channel 3.
OE4#
30
I, S, PD
Output Enable for channel 4, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 4.
HIGH: disable output channel 4.
OE5#
31
I, S, PD
Output Enable for channel 5, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 5.
HIGH: disable output channel 5.
OE6#
37
I, S, PD
Output Enable for channel 6 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 6.
HIGH: disable output channel 6.
OE7#
41
I, S, PD
Output Enable for channel 7 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 7.
HIGH: disable output channel 7.
SMBUS AND SMBUS ADDRESS
CDCDB803
SNAS820A – AUGUST 2021 – REVISED MAY 2022
www.ti.com
4
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