AMC131M02 datasheet(41/89 Pages) TI

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for 32-bit communication available for ADC data that are configured by the WLENGTH[1:0] bits in the MODE

8.5.1.9 Short SPI Frames

The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and

no ADC data are being output by the device. Read out all expected output data words from each sample period

if the ADCs are enabled. Reading all data output with each frame ensures predictable DRDY pin behavior. If

reading out all data on each output data period is not feasible, see the Collecting Data for the First Time or After

a Pause in Data Collection section on how to begin reading data again after a pause from when the ADCs were

last enabled.

A short frame is not possible when using the RESET command. A full frame must be provided for a device reset

to take place when providing the RESET command.

8.5.1.10 Communication Cyclic Redundancy Check (CRC)

The AMC131M02 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate

SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all

words in the SPI frame where the CRC is enabled, including zero-padded or sign-extended bits.

CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the

MODE register. Input CRC is disabled by default. The device checks the provided input CRC against the CRC

generated based on the input data. A CRC error occurs if the CRC words do not match. The device does not

execute any commands, except for the WREG command, if the input CRC check fails. A WREG command

always executes even when the CRC check fails. The device sets the CRC_ERR bit in the STATUS register for

all cases of a CRC error. The response on the output in the SPI frame following the frame where the CRC error

occurred is that of a NULL command, which means the STATUS register plus the conversion data are output in

the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is output.

Output CRC is not optional and always appears at the end of the output frame. The host can ignore the data if

output CRC is not used.

There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting

determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE

bit in the MODE register. Table 8-9 lists the details of the two CRC types.

The CRC calculation is initialized with the seed value of FFFFh to detect errors in the event that DIN or DOUT

are stuck low.

Table 8-9. CRC Types

CRC TYPE

POLYNOMIAL

BINARY POLYNOMIAL

CCITT CRC

x16 + x12 + x5 + 1

0001 0000 0010 0001

ANSI CRC

x16 + x15 + x2 + 1

1000 0000 0000 0101

8.5.1.11 SPI Timeout

The AMC131M02 features an SPI timeout as a means to recover SPI communication, especially in situations

where CS is permanently tied low. Enable the SPI timeout using the TIMEOUT bit in the MODE register. When

enabled, the entire SPI frame (first SCLK to last SCLK) must complete in 215 MCLK cycles, otherwise the SPI

logic resets. When a timeout happens, the device starts interpreting the data starting with the next SCLK as a

new SPI frame.

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AMC131M02

SBASA56 – SEPTEMBER 2023

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