ATTINY13 datasheet(25/177 Pages) ATMEL

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ATtiny13

2535G–AVR–01/07

128 kHz Internal

Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz.

The frequency is nominal at 3V and 25

°C. This clock may be select as the system clock

by programming the CKSEL Fuses to “11”.

When this clock source is selected, start-up times are determined by the SUT Fuses as

shown in Table 8.

System Clock Prescaler

The ATtiny13 system clock can be divided by setting the Clock Prescale Register –

CLKPR. This feature can be used to decrease power consumption when the require-

ment for processing power is low. This can be used with all clock source options, and it

will affect the clock frequency of the CPU and all synchronous peripherals. clk

I/O, clkADC,

clk

CPU, and clkFLASH are divided by a factor as shown in Table 9.

Clock Prescale Register –

CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The

CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to

zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS

bits are written. Rewriting the CLKPCE bit within this time-out period does neither

extend the time-out period, nor clear the CLKPCE bit.

• Bits 6..4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal

system clock. These bits can be written run-time to vary the clock frequency to suit the

application requirements. As the divider divides the master clock input to the MCU, the

speed of all synchronous peripherals is reduced when a division factor is used. The divi-

sion factors are given in Table 9.

To avoid unintentional changes of clock frequency, a special write procedure must be

followed to change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits

in CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to

CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write pro-

cedure is not interrupted.

Table 8. Start-up Times for the 128 kHz Internal Oscillator

SUT1..0

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset

Recommended Usage

6 CK

14CK

BOD enabled

6 CK

14CK + 4 ms

Fast rising power

6 CK

14CK + 64 ms

Slowly rising power

Reserved

Bit

210

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

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