ATTINY13 datasheet(39/177 Pages) ATMEL

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ATtiny13

2535G–AVR–01/07

Watchdog Timer Control

• Bit 7 - WDTIF: Watchdog Timer Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is

configured for interrupt. WDTIF is cleared by hardware when executing the correspond-

ing interrupt handling vector. Alternatively, WDTIF is cleared by writing a logic one to the

flag. When the I-bit in SREG and WDTIE are set, the Watchdog Time-out Interrupt is

executed.

• Bit 6 - WDTIE: Watchdog Timer Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog

Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog

Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the

Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first

time-out in the Watchdog Timer will set WDTIF. Executing the corresponding interrupt

vector will clear WDTIE and WDTIF automatically by hardware (the Watchdog goes to

System Reset Mode). This is useful for keeping the Watchdog Timer security while

using the interrupt. To stay in Interrupt and System Reset Mode, WDTIE must be set

after each interrupt. This should however not be done within the interrupt service routine

itself, as this might compromise the safety-function of the Watchdog System Reset

mode. If the interrupt is not executed before the next time-out, a System Reset will be

applied.

Note:

1. WDTON Fuse set to “0“ means programmed and “1“ means unprogrammed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the

WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when

WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple

resets during conditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

Bit

7654

321

WDTIF

WDTIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

0000

Table 16. Watchdog Timer Configuration

WDTON(1)

WDE

WDTIE

Mode

Action on Time-out

100

Stopped

None

Interrupt Mode

Interrupt

System Reset Mode

Reset

111

Interrupt and System

Reset Mode

Interrupt, then go to

System Reset Mode

Reset

ATTINY13 Datasheet(PDF) 39 Page - ATMEL Corporation

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