| Electronic Components Datasheet Search |
|
A3980 Datasheet(PDF) 12 Page - Allegro MicroSystems |
|
|
|||||||||||||||||||||||||||||
A3980 Datasheet(HTML) 12 Page - Allegro MicroSystems |
|
12 / 18 page ![]() Automotive DMOS Microstepping Driver with Translator A3980 12 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com mixed decay mode, as shown in figures 5 through 8. As the trip point is reached, the A3980 goes into fast decay mode until the voltage on the RC pin decays to the same level as the voltage applied to the PFD pin. The duration of time that the bridge operates in fast decay mode, tFD (ns), is estimated by tFD = RT × CT× ln[0.6 (VDD ⁄ VPFD)] over a range of values from CT= 470 pF to 1500 pF and from RT = 12 kΩ to 100 kΩ. After this fast decay period, the A3980 switches to slow decay mode for the remainder of the fixed off-time period. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed-off-time cycle, load current recirculates according to the decay mode selected by the control logic. The synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low DMOS RDSON. This reduces power dissipation significantly, and eliminates the need for external Schottky diodes. Synchronous rectification has two modes: Active mode and Disabled mode (described below). Active Mode. When the input on the SR terminal is set at logic low, Active mode is enabled. This mode allows synchronous rectification to occur, but when a zero current level is detected, it also prevents reversal of the load current by turning off synchronous rectification. This prevents the motor winding from conducting in the reverse direction. Disabled Mode. When the input on the SR terminal is set at logic high, Disabled mode takes effect. This mode disables synchronous rectification. This mode is typically used when external diodes are required to transfer power dissipation from the A3980 package to the external diodes. Shutdown. In the event of an overtemperature fault or an undervoltage fault on VREG, the DMOS outputs of the A3980 are disabled until the fault condition is removed. In the case of an overvoltage fault, the sink DMOS FETs are switched on, and the source FETs off. At power-up, and in the event of low VDD, the UVLO circuit disables the DMOS outputs until VDD reaches the minimum level. Once VDD is above the minimum level, the translator resets to the Home state and the DMOS outputs are re-enabled. Thermal Protection. All drivers are turned off when the junction temperature reaches the thermal shutdown value, typically 170 °C. This is intended only to protect the A3980 from failures due to excessive junction temperatures. Ther- mal protection will not protect the A3980 from continuous short circuits, and additional fault diagnostics are integrated for this purpose. Thermal shutdown has a hysteresis of approxi- mately 15 °C. Diagnostic Features. The A3980 includes monitor circuits that can detect shorts to VBB, shorts to ground, and shorted or open circuit load. Short circuits are detected by monitoring the voltage across the driving DMOS FETs and the open load is detected by monitoring the phase current when the motor is in the Home microstep position. All fault detection takes place following a delay after the blank time. Short to VBB. A short from any of the motor connections to the battery or VBB connection is detected by monitoring the voltage across the bottom FETs in each full-bridge. When the FET is on, the voltage should be no greater than the VDSLT value defined in the Electrical Characteristics table. Short to Ground. A short from any of the motor connec- tions to ground is detected by monitoring the voltage across the top FETs in each full-bridge. When the FET is turned on, the voltage should be no greater than the VDSHT value defined in the Electrical Characteristics table. Shorted Load. A short across the load is detected by monitoring the voltage across both the top and bottom FETs in each full-bridge. Short Fault Operation. Because motor capacitance may cause the measured voltages to show a fault as the full-bridge switches, voltages are not sampled until after the blank time plus an internally-generated delay, tSCT. Once a short circuit has been detected, all outputs for the faulty phase are disabled until the next step command. At the next step com- mand, the outputs are re-enabled and the voltage across the FET is resampled. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |