Automotive DMOS Microstepping Driver

with Translator

A3980

18

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Pacakge LP, 28-Pin TSSOP with Exposed Thermal Pad

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

Copyright©2003, 2006 Allegro MicroSystems, Inc.

A

1.20

MAX

.047

0.15

0.00

.006

.000

0.30

0.19

.012

.007

4.5

4.3

.177

.169

6.6

6.2

.260

.244

5.1

NOM

.200

3

NOM

.118

0.20

0.09

.008

.004

8º

0º

0.75

0.45

.030

.018

1

REF

.039

9.8

9.6

.386

.378

C

SEATING

PLANE

A

B

28X

0.10 [.004] M C

A

B

C

0.10 [.004]

28X

0.65 .026

0.25 .010

5.9

NOM

.232

0.45

NOM

.018

0.65

NOM

.026

1.85

NOM

.073

5.1

NOM

.200

3

NOM

.118

2X0.20±0.05

MIN

.008±.002

26X0.20±0.05

MIN

.008±.002

2

1

28

GAUGE PLANE

SEATING PLANE

B

A Terminal #1 mark area

B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling

Preliminary dimensions, for reference only

(reference JEDEC MO-153 AET)

Dimensions in millimeters

U.S. Customary dimensions (in.) in brackets, for reference only

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

C Reference land pattern layout (reference IPC7351

TSOP65P640X120-29M); adjust as necessary to meet application

process requirements and PCB layout tolerances; when

mounting on a multilayer PCB, thermal vias at the exposed

thermal pad land can improve thermal dissipation

(reference EIA/JEDEC Standard JESD51-5)

28

2

1

C