BK2535 datasheet(69/133 Pages) BEKEN

69 / 133 page

BK2535 datasheet

Proprietary and Confidential

Page 69 of 133

Note: If an error occurs during the reception, FSM will stay into “SEND STOP”

state until MSTAT0 register had been read by the CPU. This read operation will

clear the STA bit of MCON register and MSTAT0 register. Since MSTAT0

“IDLE” state.

Note： Due to the size of the receive buffer (1 byte), the first received data byte

is also the last data byte. So, only one byte can be read from slave in one I2C

process.

6.5.1.10.

Data Handling

The Data Bytes exchanged on the I2C line are available in MRXBUF (received

data) and MTXBUF (transmitted data) registers.

It is up to the user of the FlipI2CM to read/write data byte exchanged on the I2C

line when they are available. This can be handled by software routine thanks to

the status flags.

6.5.1.11.

Software Reset

The software reset is activated by CPU setting bit SRST of control register

(MCON). The software reset is used to stop current access on I2C bus.

Software reset initializes MCON, MSTAT0 registers and also TXRX controller.

If a software reset occurs during an I2C access, the master controller finishes the

transmit or reception of current data byte, it send a Stop condition (in case of

reception, send a ”not acknowledge" first) and next, MCON and MSTAT0

registers and TXRX controller are cleared.

At the end of software reset process, the master controller is ready to restart a

new or the same access. For same access, the CPU must refill TXBUF (for

transmission only) and set STA (MCADDR register is not affected by software

reset).

6.5.2.

I2C slave

6.5.2.1. Overview

This I2C Slave controller handles all functions necessary to respond to a request

from an I2C master controller.

Main features

Support fast and standard transfer rates.

7-bit addressing on I2C.

BK2535 Datasheet(PDF) 69 Page - Beken Corporation