EMC6D103S datasheet(74/84 Pages) SMSC

74 / 84 page

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Datasheet

Revision 0.2 (06-14-06)

SMSC EMC6D103S

DATASHEET

Notes:

Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.

All TACH inputs must be associated with a PWM output. If the tach is not being driven by the

associated PWM output it should be configured to operate in Mode 1 and the associated TACH

interrupt must be disabled.

8.2.26

These registers become read only when the Lock bit is set. Any further attempts to write to these

registers shall have no effect.

This register is used to enable individual thermal error events to set the corresponding status bits in

the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP),

which is used to enable thermal events to force the interrupt pin (INT#) low if interrupts are enabled

(see Bit[2] INTEN of the Special Function register at offset 7Ch).

See Figure 6.3 Interrupt Control on page 25.

This register contains the following bits:

Table 8.49 PWM Assignment Bit Combinations

Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6]

PWM Associated With Tachx

PWM1

PWM2

PWM3

Reserved

Table 8.50 Register 82h: Interrupt Enable 3 Register

Address

Read/

Write

Name

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

82h

R/W

Interrupt Enable 3 (Temp)

RES

D2EN

D1EN

AMB

TEMP

0Eh

Table 8.51 Interrupt Enable 3 Register Bits

BIT

NAME

R/W DEFAULT

DESCRIPTION

TEMP

R/W

Group Temperature enable bit - when set, allows Temperature channels

to assert the INT# pin.

AMB

R/W

When set, enables the ambient temperature monitor to update the status

registers and generate interrupts.

D1EN

R/W

When set, enables the Remote Diode 1 temperature monitor to update

the status registers and generate interrupts.

D2EN

R/W

When set, enables the Remote Diode 2 temperature monitor to update

the status registers and generate interrupts.

RES

R/W

Reserved

RES

R/W

Reserved

RES

R/W

Reserved

RES

R/W

Reserved

EMC6D103S Datasheet(PDF) 74 Page - SMSC Corporation

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