EMC6D103S datasheet(77/84 Pages) SMSC

77 / 84 page

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Datasheet

SMSC EMC6D103S

Revision 0.2 (06-14-06)

DATASHEET

Table 8.55 PWM Option Register Bits

BIT

NAME

R/W DEFAULT

DESCRIPTION

UPDT0

R/W

Determines the update rate of tachometer circuits associated with this

PWM driver.

00 - once a second

01 - twice a second

1x - every 300msec.

UPDT1

R/W

SZEN

R/W

Snap to Zero - determines if the PWM output ramps down to 00hor if is

immediately set to 00h when the input is set to 00h.

‘0’ - Step down the PWM output to OFF at the programmed ramp rate.

‘1’ - Transition PWM output to OFF immediately when the duty cycle is

set to 00h.

GRD0

R/W

Sets the Guard time that the tachometer associated with this PWM driver

will wait after a transition from low to high before it begins measuring.

00 = 63 clocks (90kHz clock ~ 700us)

01 = 32 clocks (90kHz clock ~356us)

10 = 16 clocks (90kHz clock ~178us)

11 = 8 clocks (90kHz clock ~89us)

GRD1

R/W

OPP

R/W

Opportunistic Mode enable - when set, enables opportunistic mode. The

tachometer reading is updated any time a valid tachometer reading can

be made. If a valid reading is detected prior to the update cycle, then the

update counter is reset.

RES

R/W

Reserved

RES

R/W

Reserved

Table 8.56 PWM/TACH Test Register Bits

BIT

NAME

R/W DEFAULT

DESCRIPTION

glitch

R/W

is used to select the glitch suppression logic on the tachometer inputs

‘0’ TACH inputs are synchronized to 90kHz oscillator.

‘1’ TACH inputs are deglitched and synchronized to 90kHz oscillator

PSYNC1

R/W

Determine how each PWM outputs exit SpinUp.

‘0’ - Exit Spinup Asynchronously to the PWM duty cycle. The first PWM

period when SpinUP is terminate may be a partial period.

‘1’ - Exit Spinup at the beginning of the next PWM duty cycle period.

This option gets rid of the initial partial period created by exiting SpinUp,

but it extends the SpinUp time beyond the programmed limit.

PSYNC2

R/W

PSYNC3

R/W

ROVR

R/W

Determines the rollover value for mode 1 (all Tachs)

‘0’ 0080h - useful for simulation

‘1’ FFFFh

PWM1_256/

R/W

Scale the PWM duty cycle for the corresponding channel. When enabled,

will shift the PWM duty cycle down by 2 creating a duty cycle with a

resolution of 1/256. This allows the device to support higher PWM

frequencies

‘0’= 64 count PWM duty cycle - resolution is 1/64

‘1’ = 256 count PWM duty cycle

PWM2_256/

R/W

PWM3_256/

R/W

EMC6D103S Datasheet(PDF) 77 Page - SMSC Corporation

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