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ISP1161 Datasheet(PDF) 44 Page - NXP Semiconductors

Part # ISP1161
Description  Full-speed Universal Serial Bus single-chip host and device controller
PDF  127 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

ISP1161 Datasheet(HTML) 44 Page - NXP Semiconductors

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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
44 of 130
9397 750 08313
© Philips Electronics N.V. 2001. All rights reserved.
When the DMA controller terminates the DMA transfer by asserting EOT and
Auto-reload mode is off, the buffer is also cleared (even if not all data are read) and
the DMA handler is disabled automatically. For the next DMA transfer, the DMA
controller as well as the DMA handler must be re-enabled. However in Auto-reload
mode, the DMA handler will automatically restart by reasserting the DREQ2 line,
without any loss of data.
11.3 Endpoint descriptions
11.3.1
Endpoints with programmable FIFO size
Each USB device is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the host and the
device. At design time each endpoint is assigned a unique number (endpoint
identifier, see Table 7). The combination of the device address (given by the host
during enumeration), the endpoint number and the transfer direction allows each
endpoint to be uniquely referenced.
The ISP1161 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable
endpoints, which can be individually defined as interrupt/bulk/isochronous, IN or OUT.
Each enabled endpoint has an associated FIFO, which can be accessed either via
the parallel I/O interface or via DMA.
11.3.2
Endpoint access
Table 7 lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is
selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Configuration
Register. A detailed description of the DMA operation is given in Section 12.
Table 7:
Endpoint access and programmability
Endpoint
identifier
FIFO size (bytes)
Double
buffering
I/O mode
access
DMA mode
access
Endpoint type
0
64 (fixed)
no
yes
no
control OUT [1]
0
64 (fixed)
no
yes
no
control IN [1]
1
programmable
supported
supported
supported
programmable
2
programmable
supported
supported
supported
programmable
3
programmable
supported
supported
supported
programmable
4
programmable
supported
supported
supported
programmable
5
programmable
supported
supported
supported
programmable
6
programmable
supported
supported
supported
programmable
7
programmable
supported
supported
supported
programmable
8
programmable
supported
supported
supported
programmable
9
programmable
supported
supported
supported
programmable
10
programmable
supported
supported
supported
programmable
11
programmable
supported
supported
supported
programmable
12
programmable
supported
supported
supported
programmable
13
programmable
supported
supported
supported
programmable
14
programmable
supported
supported
supported
programmable



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