ISP1161 datasheet(18/127 Pages) PHILIPS

18 / 127 page

Philips Semiconductors

ISP1161

Full-speed USB single-chip host and device controller

Product data

Rev. 01 — 3 July 2001

18 of 130

9397 750 08313

microprocessor must still issue a RD or WR signal to ISP1161’s RD or WR pin.

(DACK Only mode does not need the RD or WR signal.) ISP1161 will repeat the DMA

cycles until it receives an EOT signal to terminate the DMA transfer.

ISP1161 supports both external EOT and internal EOT signals. The external EOT

signal is received as input from ISP1161’s EOT pin: it generally comes from the

external microprocessor. The internal EOT signal is generated by ISP1161 internally.

To select either, set the DMA conﬁguration registers. For example, for the HC, setting

bit 2 of the HcDMAConﬁguration register (21H - Read, A1H - Write) to 1 will enable

the DMA counter for DMA transfer. When the DMA counter reaches the value of

HcTransferCounter register, the internal EOT signal will be generated to terminate the

DMA transfer.

ISP1161 supports either single-cycle burst mode DMA operation or multiple-cycle

burst mode DMA operation.

In both ﬁgures, the DMA transfer is conﬁgured such that DREQ is active HIGH and

DACK is active LOW.

N = 1/2 byte count of transfer data.

Fig 18. DMA transfer for single-cycle burst mode.

MGT942

DREQ

DACK

D[15:0]

EOT

data #1

data #2

data #N

RD or WR

N = 1/2 byte count of transfer data, K = number of cycles/burst.

Fig 19. DMA transfer for multi-cycle burst mode.

MGT943

data #1

data #K

data #2K

data #N

data #(K

+1)

data #(N

−K+1)

DREQ

DACK

D[15:0]

EOT

RD or WR

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