ISP1161 datasheet(8/127 Pages) PHILIPS

8 / 127 page

Philips Semiconductors

ISP1161

Full-speed USB single-chip host and device controller

Product data

Rev. 01 — 3 July 2001

8 of 130

9397 750 08313

I/O

bit 6 of bidirectional data; slew-rate controlled; TTL input;

three-state output

I/O

bit 7 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

digital ground

I/O

bit 8 of bidirectional data; slew-rate controlled; TTL input;

three-state output

I/O

bit 9 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D10

I/O

bit 10 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D11

I/O

bit 11 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D12

I/O

bit 12 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D13

I/O

bit 13 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

digital ground

D14

I/O

bit 14 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D15

I/O

bit 15 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

digital ground

Vhold1

voltage holding pin; this pin is internally connected to the

Vreg(3.3) and Vhold2 pins. When the VCC pin is connected to

+5 V, this pin will output 3.3 V, hence it should not be

connected to +5 V. When the VCC pin is connected to

+3.3 V, this pin can either be connected to +3.3 V or left

unconnected. In all cases this pin should be decoupled to

DGND.

n.c.

no connection

chip select input

read strobe input

write strobe input

Vhold2

voltage holding pin; this pin is internally connected to the

Vreg(3.3) and Vhold1 pins. When the VCC pin is connected to

+5 V, this pin will output 3.3 V, hence it should not be

connected to +5 V. When the VCC pin is connected to

+3.3 V, this pin can either be connected to +3.3 V or left

unconnected. In all cases this pin should be decoupled to

DGND.

DREQ1

HC’s DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161 wants to start a

DMA transfer; see HcHardwareConﬁguration register

(20H/A0H)

Table 2:

Pin description for LQFP64 …continued

Symbol [1]

Type

Description

ISP1161 Datasheet(PDF) 8 Page - NXP Semiconductors

ISP1161 Datasheet(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL