AM29LV033C datasheet(18/49 Pages) AMD

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Am29LV033C

22268B5 September 12, 2006

DA TA

SH EET

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadver tent writes (refer to Table 9, on

page 25 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent ac-

cidental erasure or programming, which might

otherwise be caused by spurious system level signals

during V

CC power-up and power-down transitions, or

from system noise.

Low VCC Write Inhibit

When V

CC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets. Subsequent writes are ignored

until VCC is greater than VLKO. The system must pro-

vide the proper signals to the control pins to prevent

unintentional writes when V

CC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V

IL and OE# = VIH during power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to reading array data on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables Table 5, on page 18 to Table 8, on

page 20. To terminate reading CFI data, the system

must write the reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Table 5 to Table 8,

on page 20. The system must write the reset com-

mand to return the device to the autoselect mode.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD represen-

tative for copies of these documents.

Table 5.

CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

51h

52h

59h

Query Unique ASCII string “QRY”

13h

14h

02h

00h

Primary OEM Command Set

15h

16h

40h

00h

Address for Primary Extended Table

17h

18h

00h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

00h

Address for Alternate OEM Extended Table (00h = none exists)

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