AM29LV033C datasheet(12/49 Pages) AMD

12 / 49 page

Am29LV033C

22268B5 September 12, 2006

DA TA

SH EET

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2, on page 13 indi-

cates the address space that each sector occupies. A

“sector address” consists of the address bits required

to uniquely select a sector. The “Command Defini-

tions” section contains details for erasing a sector or

the entire chip, or suspending/resuming the erase op-

eration.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” on page 15

and “Autoselect Command Sequence” on page 21

sections for more information.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” on page 34 section contains timing

specification tables and timing diagrams for write oper-

ations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the ACC pin. This function is primarily in-

tended to allow faster manufacturing throughput at the

factory.

If the system asserts VHH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system then

uses a two-cycle program command sequence as re-

quired by the Unlock Bypass mode. Removing VHH

from the ACC pin returns the device to normal opera-

tion. Note that the ACC pin must not be at VHH for op-

erations other than accelerated programming, or

device damage may result.

Program and Erase Operation Status

During an erase or program operation, the system

checks the status of the operation by reading the sta-

tus bits on DQ7–DQ0. Standard read cycle timings

and I

CC read specifications apply. Refer to “Write Op-

eration Status” on page 26 for more information, and

to “AC Characteristics” on page 34 for timing dia-

grams.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

CC ± 0.3 V.

(Note that this is a more restricted voltage range than

IH.) If CE# and RESET# are held at VIH, but not within

CC ± 0.3 V, the device is in the standby mode, but the

standby current is greater. The device requires stan-

dard access time (t

CE) for read access when the de-

vice is in either of these standby modes, before it is

ready to read data.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

CC3 in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

t AC C + 30 n s. The automatic sleep mode is

independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new

data when addresses are changed. While in sleep

mode, output data is latched and always available to

the system. ICC4 in the DC Characteristics table

repr esen ts th e automatic sleep mo de cu rren t

specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current is

greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would also reset the Flash mem-

ory, enabling the system to read the boot-up firmware

from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

AM29LV033C Datasheet(PDF) 12 Page - Advanced Micro Devices

AM29LV033C Datasheet(HTML) 12 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL