MBM29F400TC datasheet(18/48 Pages) SPANSION

18 / 48 page

MBM29F400TC-55/-70-90/MBM29F400BC-55/-70-90

Write Operation Status

*1 : Performing successive read operations from any address will cause DQ6 to toggle.

*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”

at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

Notes:

• DQ0 and DQ1 are reserve pins for future use. DQ4 is Fujitsu internal use only.

• DQ15 to DQ8 are “DON’T CARES” because there is for × 16 mode.

DQ7

Data Polling

The MBM29F400TC/BC device feature Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device

will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart

for Data Polling (DQ7) is shown in “Data Polling Algorithm” in sFLOW CHART.

For Programing, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased

and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is

close to being completed, the MBM29F400TC/BC data pins (DQ7) may change asynchronously while the output

enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of

time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7

output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation

and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will

be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm

or sector erase time-out (See “Hardware Sequence Flags”).

See “AC Waveforms for Data Polling during Embedded Algorithm Operations” in sTIMING DIAGRAM for the

Data Polling timing specifications and diagrams.

Hardware Sequence Flags

Status

DQ7

DQ6

DQ5

DQ3

DQ2

Progress

Embedded Program Algorithm

DQ7

Toggle

Embedded Erase Algorithm

Toggle

Erase

Suspended

Mode

Erase Suspend Read

(Erase Suspended Sector)

Toggle

Erase Suspend Read

(Non-Erase Suspended Sector)

Data

Erase Suspend Program

(Non-Erase Suspended Sector)

DQ7

Toggle*1

1*2

Exceeded

Time

Limits

Embedded Program Algorithm

DQ7

Toggle

Embedded Erase Algorithm

Toggle

N/A

Erase

Suspended

Mode

Erase Suspend Program (Non-Erase

Suspended Sector)

DQ7

Toggle

N/A

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