LTM4686B datasheet(19/132 Pages) AD

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LTM4683

Rev. 0

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of the pin state. Note that using RCONFIGs on VOUT0_

CFG/VTRIM0_CFG can affect the VOUT0 range setting

(MFR_PWM_MODE0[1]) and loop gain. For addressed

ASEL_01, Page 0x00 corresponds to Channel 0, and Page

0x01 corresponds to Channel 1. See PAGE command

description section.

SCL_01, SCL_23 (D10, W9): Serial Bus Clock Open-Drain

Input (Can Be an Input and Output, if Clock Stretching

is Enabled). A pull-up resistor to 3.3V is required in the

application for digital communication to the SMBus main

device(s) that nominally drive this clock. The LTM4683

will never encounter scenarios where it would need to

engage clock stretching unless serial clock line (SCL)

communication speeds exceed 100kHz—and even then,

LTM4683 will not clock stretch unless clock stretching

is enabled by using the setting MFR_CONFIG_ALL[1] =

1b. The factory-default NVM configuration setting has

MFR_CONFIG_ALL[1] = 0b: clock stretching disabled.

If communication on the bus at clock speeds above

100kHz is required, the user’s SMBus main device(s)

needs to implement clock stretching support to ensure

solid serial bus communications, and only, then should

MFR_CONFIG_ALL[1] be set to 1b. When clock stretch-

ing is enabled, SCL becomes a bidirectional, open-drain

output pin on the LTM4683.

SYNC_01, SYNC_23 (D11, V9): External Clock

Synchronization Input and Open-Drain Output Pin. If an

external clock is present at this pin, the switching fre-

quency will be synchronized to the external clock. If the

main clock mode is enabled, this pin will pull low at the

switching frequency with a 500ns pulse to the ground. A

resistor pull-up to 3.3V is required in the application if the

LTM4683 is the main device.

VDD33_01 (E8): Internally Generated 3.3V Power Supply

Output Pin for Channel 0 and Channel 1 Circuits. This pin

should only be used to provide external current for the

pull-up resistors required for FAULTn, SHARE_CLK_nn,

and SYNC_nn, and may be used to provide external cur-

rent for pull-up resistors on RUNn, SDA_nn, SCL_nn,

ALERT_nn and PGOODn. Where nn is either 0,1 or 2,3

channels, and n is the actual channel. No external decou-

pling is required. VDD33_01 is powered from VBIAS, that

programming RUNn improves efficiency.

WP_01, WP_23 (E9, Y11): Write Protect Pin, Active High.

An internal 10µA current source pulls this pin to VDD33. If

WP is open circuit or logic high, only I2C writes to PAGE,

OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and

MFR_EE_UNLOCK are supported. Additionally, Individual

faults can be cleared by writing 1b’s to bits of interest in

registers prefixed with STATUS. If WP is low, I2C writes

are unrestricted.

TSNS0, TSNS1, TSNS2, TSNS3 (E11, E10, U8, U9):

Power stage temperature monitors for the four channels.

See the Applications Information section.

VOSNS1– (F8): Channel 1 Negative Differential Voltage

Sense Input. See VOSNS1+.

SGND01, SGND23 (F10-F11, U10-U11): SGND is the sig-

nal ground return path of the LTM4683 internal control-

lers. SGND is not internally connected to GND. Connect

SGND to GND local to the LTM4683. See the Layout

Checklist/Example section.

VOUT1 (F13-F15, G13-G15, H13-H15, J13-J15, K13-

K15): Channel 1 Output Voltage. Place recommended

output capacitors from this output copper shape to GND.

See the Layout Checklist/Example section.

SW1 (G1-G2, H1-H2, J1-J2): Switching Node of Channel 1

Step-Down Converter Stage. Used for test purposes or

EMI-snubbing. It may be routed a short distance to a local

test point to monitor the switching action of channel 1,

if desired, but do not route near any sensitive signals.

Otherwise, leave it open.

VOSNS1+ (G8): Channel 1 Positive Differential Voltage

Sense Input. Together, VOSNS1+ and VOSNS1– serve to

Kelvin-sense the VOUT1 output voltage at VOUT1’s point-

of-load (POL) and provide the differential feedback signal

directly to channel 1’s feedback loop. Command VOUT1’s

target regulation voltage by serial bus. Its initial command

value at SVIN_01 power-up is dictated by NVM contents

(factory default: 0.5V)—or, optionally, may be set by con-

figuration resistors; see VOUT1_CFG, VTRIM1_CFG and

the Applications Information section.

COMP0b, COMP1b, COMP2b, COMP3b (G10, F9, T9,

W11): Current Control Threshold and Error Amplifier

Compensation Nodes. Each associated channel’s current

PIN FUNCTIONS

LTM4686B Datasheet(PDF) 19 Page - Analog Devices

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